Editing Motorola 6800 (section)

=== MOS ICs ===
[[File:Silicon wafer.jpg|thumb|upright=.75 | A silicon wafer holding many integrated circuit chips]]

The first-generation metal–oxide–semiconductor (MOS) chips used p-channel field-effect transistors, known as p-channel [[MOSFET]]s (p-channel describes the configuration of the transistor). These ICs were used in calculators and in the first microprocessor, the Intel 4004. They were easy to produce but were slow and difficult to interface to the popular [[Transistor–transistor logic|TTL]] digital logic ICs. An n-channel MOS integrated circuit could operate two or three times faster and was compatible with TTL. They were much more difficult to produce because of an increased sensitivity to contamination that required an ultra clean production line and meticulous process control.<ref name = "Verhofstadt 1976">{{Cite journal | last = Verhofstadt | first = Peter | title = Evaluation of technology options for LSI processing elements | journal = Proceedings of the IEEE | volume = 64 | issue = 6 | pages =842–851 | publisher = IEEE | date = June 1976 | doi = 10.1109/PROC.1976.10234 | s2cid = 28259688 }}</ref> Motorola did not have an n-channel MOS production capability and had to develop one for the 6800 family.

Motorola's n-channel MOS test integrated circuits were complete in late 1971 and these indicated the clock rate would be limited to 1&nbsp;MHz. These used "[[enhancement-mode]]" MOS transistors. There was a newer fabrication technology that used "[[depletion-mode]]" MOS transistors as loads, which would allow smaller and faster circuits (this was also known as [[depletion-load nMOS]]). The "depletion-mode" processing required extra steps so Motorola decided to stay with "enhancement-mode" for the new single-supply-voltage design. The 1&nbsp;MHz clock rate meant the chip designers would have to come up with several architectural innovations to speed up the microprocessor throughput.<ref name ="Bennett 3962682"/> These resulting circuits were faster but required more area on the chip.<ref>Motorola 6800 Oral History (2008), p. 27</ref>

In the 1970s, semiconductors were fabricated on 3 inch (75&nbsp;mm) diameter [[Wafer (electronics)|silicon wafers]]. Each wafer could produce 100 to 200 integrated circuit chips or dies. The technical literature would state the length and width of each chip in "mils" (0.001 inch). The current industry practice is to state the chip area. Processing wafers required multiple steps and flaws would appear at various locations on the wafer during each step. The larger the chip the more likely it would encounter a defect. The percentage of working chips, or yield, declined steeply for chips larger than 160 mils (4&nbsp;mm) on a side.

The target size for the 6800 was 180 mils (4.6&nbsp;mm) on each side but the final size was 212 mils (5.4&nbsp;mm) with an area of 29.0&nbsp;mm<sup>2</sup>. At 180 mils, a {{convert|3|in|mm|adj=on}} wafer will hold about 190 chips, 212 mils reduces that to 140 chips. At this size the yield may be 20% or 28 chips per wafer.<ref name = "Chip Yield">{{Cite journal | last = Wikes | first = W. E. | title = A Microprocessor Chip Designed with the User in Mind | journal = Computer | volume = 10 | issue = 1 | pages =18–22 | publisher = IEEE | date = January 1977 | doi = 10.1109/C-M.1977.217492| s2cid = 11802783 }} This paper describes the Electronic Arrays [[EA9002]] microprocessor that was 200 by 200 mils and fabricated on a 3 inch silicon wafer.</ref><ref name = "Elmasry 1981">{{Cite book | editor-last = Elmasry | editor-first = Mohamed I. | title = Digital MOS integrated circuits | publisher = IEEE Press | year = 1981 | isbn = 978-0-87942-152-6 }} A 3-inch wafer can hold 200 dies of 160 by 160 mils. Total yield is Wafer yield x Assembly yield x Final test yield. In 1976 this was 40% x 80% x 85% or 26%. A 3 inch wafer with 200 die would yield 54 working microprocessors.</ref> The Motorola 1975 annual report highlights the new MC6800 microprocessor but has several paragraphs on the "MOS yield problems."<ref name = "Motorola 1975 Report"/> <!-- Page 15 -->

The yield problem was solved with a design revision started in 1975 to use depletion mode in the M6800 family devices. The 6800 die size was reduced to 160 mils (4&nbsp;mm) per side with an area of 16.5&nbsp;mm<sup>2</sup>. This also allowed faster clock speeds, the MC68A00 would operate at 1.5&nbsp;MHz and the MC68B00 at 2.0&nbsp;MHz. The new parts were available in July 1976.<ref name = "Daniels 1996">{{Cite journal | last = Daniels | first = R. Gary | title = A Participant's Perspective | journal = IEEE Micro | volume = 16 | issue = 5 | pages = 21–31 | publisher = IEEE Computer Society | date = December 1996 | doi = 10.1109/40.546562 | s2cid = 26787252 }} Daniels, "My first assignment was to lead a small team to redesign the 6800 MPU to make it more manufacturable and so that higher speed versions could be selected."</ref><ref name = "MC6800D March 1976">{{Cite journal | title = Electronics Newsletter: 6800 gains speed, lower prices by summer | journal = Electronics | volume = 49 | issue = 5 | page =25 | publisher = McGraw-Hill | location = New York | date = March 4, 1976}}</ref>