Editing Itanium (section)

=== Itanium (Merced): 2001 ===
{{Infobox CPU
 | name=Itanium (Merced)
 | image=KL Intel Itanium ES.jpg
 | image_size=300px
 | caption=Itanium processor
 | produced-start=29 May–June 2001
 | produced-end=10 April 2003<ref>{{cite web |title=Product Change Notification |url=http://developer.intel.com/design/pcn/Processors/D0102840.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040719063719/http://developer.intel.com/design/pcn/Processors/D0102840.pdf |archive-date=2004-07-19}}</ref>
 | slowest=733
 | slow-unit=
 | fastest=800
 | fast-unit=MHz
 | fsb-slowest=266
 | fsb-slow-unit=MT/s
 | manuf1=Intel
 | core1=
 | size-from=
 | size-to=
 | arch=
 | sock1=[[PAC418]]
 | numcores=1
 | l2cache=96&nbsp;KB
 | l3cache=2 or 4&nbsp;MB
}}
After having sampled 40,000 chips to the partners, Intel launched Itanium on May 29, 2001, with first OEM systems from HP, IBM and Dell shipping to customers in June.<ref>{{cite web |last1=Niccolai |first1=James (IDG News Service) |title=Intel officially launches 64-bit Itanium chip |url=https://www.computerworld.com/article/2582076/intel-officially-launches-64-bit-itanium-chip.html |website=[[Computerworld]] |date=29 May 2001 |access-date=30 March 2022}}</ref><ref>{{cite web |title=Server makers tout Itanium models |url=https://www.zdnet.com/article/server-makers-tout-itanium-models-5000117490/ |website=[[ZDNet]] |access-date=30 March 2022}}</ref> By then Itanium's performance was not superior to competing RISC and CISC processors.<ref>{{cite magazine
 | author=Linley Gwennap
 | title=Itanium era dawns
 | url=https://www.eetimes.com/itanium-era-dawns/
 | magazine=EE Times
 | date=June 4, 2001
 | access-date=December 17, 2019
 | archive-date=December 17, 2019
 | archive-url=https://web.archive.org/web/20191217201629/https://www.eetimes.com/itanium-era-dawns/
 | url-status=live
 }}</ref>
Itanium competed at the low-end (primarily four-[[central processing unit|CPU]] and smaller systems) with servers based on [[x86]] processors, and at the high-end with [[IBM Power microprocessors|IBM POWER]] and [[Sun Microsystems]] [[SPARC]] processors. Intel repositioned Itanium to focus on the high-end business and [[High-performance computing|HPC]] computing markets, attempting to duplicate the x86's successful "horizontal" market (i.e., single architecture, multiple systems vendors). The success of this initial processor version was limited to replacing the [[PA-RISC]] in HP systems, [[DEC Alpha|Alpha]] in Compaq systems and [[MIPS architecture|MIPS]] in [[Silicon Graphics|SGI]] systems, though IBM also delivered a supercomputer based on this processor.<ref name="Thunder">{{cite web
 | url=http://www.top500.org/system/ranking/5597
 | title=Titan Cluster Itanium 800&nbsp;MHz
 | access-date=May 16, 2007
 | work=[[TOP500]] web site
 | archive-date=September 25, 2006
 | archive-url=https://web.archive.org/web/20060925041933/http://www.top500.org/system/ranking/5597
 | url-status=dead
 }}</ref>
POWER and SPARC remained strong, while the [[32-bit computing|32-bit]] x86 architecture continued to grow into the enterprise space, building on the economies of scale fueled by its enormous installed base.

Only a few thousand systems using the original ''Merced'' Itanium processor were sold, due to relatively poor performance, high cost and limited software availability.<ref>{{cite news
 | author=Michael Kanellos
 | title=Itanium sales off to a slow start
 | url=https://www.cnet.com/tech/tech-industry/itanium-sales-off-to-a-slow-start/
 | work=CNET News
 | date=December 11, 2001
 | access-date=July 4, 2023
 }}</ref> Recognizing that the lack of software could be a serious problem for the future, Intel made thousands of these early systems available to independent software vendors (ISVs) to stimulate development. HP and Intel brought the next-generation Itanium&nbsp;2 processor to the market a year later. Few of the microarchitectural features of Merced would be carried over to all the subsequent Itanium designs, including the 16+16 KB L1 cache size and the 6-wide (two-bundle) instruction decoding.