Editing Fast Ethernet (section)

=== 100BASE-T2 === <!-- This section is linked from [[Ethernet over twisted pair]] -->
{| class="wikitable" style="float: right; margin: 0 0 1em 1em;"
|+ 100BASE-T2 symbols to [[PAM-5]] line modulation level mapping
|-
! Symbol !! Line signal level
|-
| 000 || 0
|-
| 001 || +1
|-
| 010 || −1
|-
| 011 || −2
|-
| 100 (ESC) || +2
|}

In '''100BASE-T2''', standardized in IEEE 802.3y, the data is transmitted over two copper pairs, but these pairs are only required to be Category 3 rather than the Category 5 required by 100BASE-TX. Data is transmitted and received on both pairs simultaneously<ref name="Breyer and Riley">{{cite book |title=Switched, Fast, and Gigabit Ethernet |author=Robert Breyer and Sean Riley |publisher=Macmillan Technical Publishing |year=1999 |page=107}}</ref> thus allowing full-duplex operation. Transmission uses 4 bits per symbol. The 4-bit symbol is expanded into two 3-bit symbols through a non-trivial scrambling procedure based on a [[linear-feedback shift register]].<ref>IEEE 802.3y</ref> This is needed to flatten the bandwidth and emission spectrum of the signal, as well as to match transmission line properties. The mapping of the original bits to the symbol codes is not constant in time and has a fairly large period (appearing as a pseudo-random sequence). The final mapping from symbols to [[PAM-5]] line modulation levels obeys the table on the right. 100BASE-T2 was not widely adopted but the technology developed for it is used in 1000BASE-T.<ref name="TDG_ETH_2nd" />