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=== Organization === PC3200 is DDR SDRAM designed to operate at 200 MHz using DDR-400 chips with a bandwidth of 3,200 MB/s. Because PC3200 memory transfers data on both the rising and falling clock edges, its effective clock rate is 400 MHz. 1 GB PC3200 non-ECC modules are usually made with 16 512 Mbit chips, 8 on each side (512 Mbits Γ 16 chips) / (8 bits (per byte)) = 1,024 MB. The individual chips making up a 1 GB memory module are usually organized as 2<sup>26</sup> 8-bit words, commonly expressed as 64MΓ8. Memory manufactured in this way is low-density RAM and is usually compatible with any motherboard specifying PC3200 DDR-400 memory.<ref>{{Cite web|url=https://superuser.com/questions/138800/per-bytes-ram-memory-acess|title=Per bytes RAM memory access|website=Super User|access-date=2018-10-21}}</ref>{{Citation needed|date=October 2010}}
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