Editing Cray-1 (section)

==Description==
[[File:Cray-1 momory board 4K words.jpg|right|thumb|Memory board, other side is the same - holds 4,096 64-bit words.]]
The new machine was the first Cray design to use [[integrated circuit]]s (ICs). Although ICs had been available since the 1960s, it was only in the early 1970s that they reached the performance necessary for high-speed applications. The Cray-1 used only four different IC types, an [[emitter-coupled logic|ECL]] dual 5-4 [[NOR gate]] (one 5-input, and one 4-input, each with differential output),<ref>Fairchild Semiconductor, [http://doc.chipfind.ru/fairchild/11c01.htm "Fairchild 11C01 ECL Dual 5-4 Input OR/NOR Gate,"] Fairchild ECL Databook, {{circa|1972}}.</ref> another slower [[emitter-coupled logic|MECL]] 10K 5-4 NOR gate used for address [[fanout]], a 16×4-bit high speed (6&nbsp;ns) [[static RAM]] (SRAM) used for registers and a 1,024×1-bit 48&nbsp;ns SRAM used for the main memory. These integrated circuits were supplied by [[Fairchild Semiconductor]] and [[Motorola]].<ref name="russell">{{cite journal |last1=Russell |first1=Richard M. |title=The CRAY-1 computer system |journal=Communications of the ACM |date=1 January 1978 |volume=21 |issue=1 |pages=63–72 |doi=10.1145/359327.359336 |s2cid=28752186 |doi-access=free }}</ref> In all, the Cray-1 contained about 200,000 gates.

ICs were mounted on large five-layer [[printed circuit board]]s, with up to 144 ICs per board. Boards were then mounted back to back for cooling (see below) and placed in twenty-four {{convert |28|in|mm|adj =mid|-high}} racks containing 72 double-boards. The typical module (distinct processing unit) required one or two boards. In all the machine contained 1,662 modules in 113 varieties.

Each cable between the modules was a [[twisted pair]], cut to a specific length in order to guarantee the signals arrived at precisely the right time and minimize electrical reflection. Each signal produced by the ECL circuitry was a differential pair, so the signals were balanced. This tended to make the demand on the power supply more constant and reduce switching noise. The load on the power supply was so evenly balanced that Cray boasted that the power supply was unregulated. To the power supply, the entire computer system looked like a simple resistor.

The high-performance [[emitter-coupled logic|ECL]] circuitry generated considerable heat, and Cray's designers spent as much effort on the design of the refrigeration system as they did on the rest of the mechanical design. In this case, each circuit board was paired with a second, placed back to back with a sheet of copper between them. The copper sheet conducted heat to the edges of the cage, where liquid [[Freon]] running in stainless steel pipes drew it away to the cooling unit below the machine. The first Cray-1 was delayed six months due to problems in the cooling system; lubricant that is normally mixed with the Freon to keep the compressor running would leak through the seals and eventually coat the boards with oil until they shorted out. New welding techniques had to be used to properly seal the tubing.

In order to bring maximum speed out of the machine, the entire chassis was bent into a large C-shape. Speed-dependent portions of the system were placed on the "inside edge" of the chassis, where the wire-lengths were shorter. This allowed the cycle time to be decreased to 12.5&nbsp;ns (80&nbsp;MHz), not as fast as the 8&nbsp;ns 8600 he had given up on, but fast enough to beat [[CDC 7600]] and the STAR. NCAR estimated that the overall throughput on the system was 4.5 times that of the CDC 7600.<ref>{{cite web|url=https://www.cisl.ucar.edu/computers/gallery/cray/cray1.jsp|title=SCD Supercomputer Gallery: CRAY1-A|publisher=National Center for Atmospheric Research|access-date=January 30, 2016|archive-url=https://web.archive.org/web/20160303175100/http://www.cisl.ucar.edu/computers/gallery/cray/cray1.jsp|archive-date=March 3, 2016|url-status=dead}}</ref>

The Cray-1 was built as a [[64-bit computing|64-bit]] system, a departure from the 7600/6600, which were 60-bit machines (a change was also planned for the 8600). Addressing was 24-bit, with a maximum of 1,048,576 64-bit words (1 megaword) of main memory, where each word also had eight parity bits for a total of 72 bits per word.<ref name="brochure">{{cite web|url=http://archive.computerhistory.org/resources/text/Cray/Cray.Cray1.1977.102638650.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://archive.computerhistory.org/resources/text/Cray/Cray.Cray1.1977.102638650.pdf |archive-date=2022-10-09 |url-status=live|title=The Cray-1 Computer System|publisher=Cray Research Inc.}}</ref> <!--24-bit address should give 16 MiB capacity--> Memory was spread across 16 [[interleaved memory]] banks, each with a 50&nbsp;ns cycle time, allowing up to four words to be read per cycle. Smaller configurations could have 0.25 or 0.5 megawords of main memory. Maximum aggregate memory bandwidth was 638&nbsp;Mbit/s.<ref name="brochure"/>

The main register set consisted of eight 64-bit scalar (S) registers and eight 24-bit address (A) registers. These were backed by a set of sixty-four registers each for S and A temporary storage known as T and B respectively, which could not be seen by the functional units. The vector system added another eight 64-element by 64-bit vector (V) registers, as well as a vector length (VL) and vector mask (VM). Finally, the system also included a 64-bit real-time clock register and four 64-bit instruction buffers that held sixty-four 16-bit instructions each. The hardware was set up to allow the vector registers to be fed at one word per cycle, while the address and scalar registers required two cycles. In contrast, the entire 16-word instruction buffer could be filled in four cycles.

The Cray-1 had twelve pipelined functional units. The 24-bit address arithmetic was performed in an add unit and a multiply unit. The scalar portion of the system consisted of an add unit, a logical unit, a [[Hamming weight|population count]], a leading zero count unit and a shift unit. The vector portion consisted of add, logical and shift units. The floating point functional units were shared between the scalar and vector portions, and these consisted of add, multiply and reciprocal approximation units.

The system had limited parallelism. It could issue one instruction per clock cycle, for a theoretical performance of 80&nbsp;[[Instructions per second|MIPS]], but with vector floating-point multiplication and addition occurring in parallel theoretical performance was 160<ref>{{cite web|url=http://www.cray.com/About/History.aspx|title=Company History - Cray|url-status=dead|archive-url=https://web.archive.org/web/20140712100729/http://www.cray.com/About/History.aspx|archive-date=July 12, 2014|df=mdy-all}}</ref>&nbsp;MFLOPS. (The reciprocal approximation unit could also operate in parallel, but did not deliver a true floating-point result - two additional multiplications were needed to achieve a full division.)

Since the machine was designed to operate on large data sets, the design also dedicated considerable circuitry to [[input/output|I/O]]. Earlier Cray designs at CDC had included separate computers dedicated to this task, but this was no longer needed. Instead the Cray-1 included four six-channel controllers, each of which was given access to main memory once every four cycles. The channels were 16 bits wide and included three control bits and four bits for error correction, so the maximum transfer speed was one word per 100&nbsp;ns, or 500 thousand words per second for the entire machine.

The initial model, the '''Cray-1A''', weighed {{convert|10500|lb|kg}} including the Freon refrigeration system. Configured with 1 million [[Word (data type)|words]] of main memory, the machine and its power supplies consumed about 115&nbsp;kW of power;<ref name="russell" /> cooling and storage likely more than doubled this figure.{{Citation needed|date=November 2010}} A [[Data General]] [[Data General Nova|SuperNova S/200]] minicomputer served as the maintenance control unit (MCU), which was used to feed the [[Cray Operating System]] into the system at boot time, to monitor the CPU during use, and optionally as a front-end computer. Most, if not all, Cray-1As were delivered using the follow-on [[Data General Eclipse]] as the MCU.

The reliability of the CRAY-1A was very low by today's standards. At the [[European Centre for Medium-Range Weather Forecasts]], which was one of the first customers, the mean time between hardware faults was reported to be 96 hours in 1979.<ref>{{cite book| title=Medium-Range Weather Prediction – the European Approach | last=Woods | first=Austin | publisher=Springer | year=2006 | isbn=978-0-387-26928-3}}</ref> Seymour Cray deliberately made design decisions that sacrificed reliability for speed, but improved his later designs after being questioned on this matter. Similarly, the Cray Operating System (COS) was fairly rudimentary, hardly tested and updated weekly or even daily in the early days.