Editing Charge-coupled device (section)

=== Design and manufacturing ===
The photoactive region of a CCD is, generally, an [[epitaxial]] layer of [[silicon]]. It is lightly ''p'' doped (usually with [[boron]]) and is grown upon a [[substrate (materials science)|substrate]] material, often p++. In buried-channel devices, the type of design utilized in most modern CCDs, certain areas of the surface of the silicon are [[ion implantation|ion implanted]] with [[phosphorus]], giving them an n-doped designation. This region defines the channel in which the photogenerated charge packets will travel. [[Simon Sze]] details the advantages of a buried-channel device:<ref name=sze />
<blockquote>This thin layer (= 0.2–0.3 micron) is fully depleted and the accumulated photogenerated charge is kept away from the surface. This structure has the advantages of higher transfer efficiency and lower dark current, from reduced surface recombination. The penalty is smaller charge capacity, by a factor of 2–3 compared to the surface-channel CCD.</blockquote> The gate oxide, i.e. the [[capacitor]] [[dielectric]], is grown on top of the epitaxial layer and substrate.

Later in the process, [[polysilicon]] gates are deposited by [[chemical vapor deposition]], patterned with [[photolithography]], and etched in such a way that the separately phased gates lie perpendicular to the channels. The channels are further defined by utilization of the [[LOCOS]] process to produce the [[channel stop]] region.

Channel stops are thermally grown [[oxide]]s that serve to isolate the charge packets in one column from those in another. These channel stops are produced before the polysilicon gates are, as the LOCOS process utilizes a high-temperature step that would destroy the gate material. The channel stops are parallel to, and exclusive of, the channel, or "charge carrying", regions.

Channel stops often have a p+ doped region underlying them, providing a further barrier to the electrons in the charge packets (this discussion of the physics of CCD devices assumes an [[electron]] transfer device, though hole transfer is possible).

The clocking of the gates, alternately high and low, will forward and reverse bias the diode that is provided by the buried channel (n-doped) and the epitaxial layer (p-doped). This will cause the CCD to deplete, near the [[p–n junction]] and will collect and move the charge packets beneath the gates—and within the channels—of the device.

CCD manufacturing and operation can be optimized for different uses. The above process describes a frame transfer CCD. While CCDs may be manufactured on a heavily doped p++ wafer it is also possible to manufacture a device inside p-wells that have been placed on an n-wafer. This second method, reportedly, reduces smear, [[dark current (physics)|dark current]], and [[infrared]] and red response. This method of manufacture is used in the construction of interline-transfer devices.

Another version of CCD is called a peristaltic CCD. In a peristaltic charge-coupled device, the charge-packet transfer operation is analogous to the peristaltic contraction and dilation of the [[digestive system]]. The peristaltic CCD has an additional implant that keeps the charge away from the silicon/[[silicon dioxide]] interface and generates a large lateral electric field from one gate to the next. This provides an additional driving force to aid in transfer of the charge packets.