Editing Cache coherence (section)

==Coherence protocols==
Coherence protocols apply cache coherence in multiprocessor systems. The intention is that two clients must never see different values for the same shared data.

The protocol must implement the basic requirements for coherence. It can be tailor-made for the target system or application.

Protocols can also be classified as snoopy or directory-based. Typically, early systems used directory-based protocols where a directory would keep a track of the data being shared and the sharers. In snoopy protocols, the transaction requests (to read, write, or upgrade) are sent out to all processors. All processors snoop the request and respond appropriately.

Write propagation in snoopy protocols can be implemented by either of the following methods:
;Write-invalidate: When a write operation is observed to a location that a cache has a copy of, the cache controller invalidates its own copy of the snooped memory location, which forces a read from main memory of the new value on its next access.<ref name=":3" />
;Write-update: When a write operation is observed to a location that a cache has a copy of, the cache controller updates its own copy of the snooped memory location with the new data.
If the protocol design states that whenever any copy of the shared data is changed, all the other copies must be "updated" to reflect the change, then it is a write-update protocol. If the design states that a write to a cached copy by any processor requires other processors to discard or invalidate their cached copies, then it is a write-invalidate protocol.

However, scalability is one shortcoming of broadcast protocols.

Various models and protocols have been devised for maintaining coherence, such as [[MSI protocol|MSI]], [[MESI protocol|MESI]] (aka Illinois), [[MOSI protocol|MOSI]], [[MOESI protocol|MOESI]], [[MERSI protocol|MERSI]], [[MESIF protocol|MESIF]], [[Write-once (cache coherence)|write-once]], Synapse, Berkeley, [[Firefly (cache coherence protocol)|Firefly]] and [[Dragon protocol]].<ref name=":1" /> In 2011, [[ARM Ltd]] proposed the AMBA 4 ACE<ref>{{Cite book|title=Formal Analysis of the ACE Specification for Cache Coherent Systems-on-Chip. In Formal Methods for Industrial Critical Systems|last=Kriouile|date=16 September 2013|publisher=Springer Berlin Heidelberg|isbn=978-3-642-41010-9}}</ref> for handling coherency in [[System on a chip|SoCs]]. The AMBA CHI (Coherent Hub Interface) specification<ref>{{Cite web|last=Ltd|first=Arm|title=AMBA {{!}} AMBA 5|url=https://developer.arm.com/architectures/system-architectures/amba/amba-5|access-date=2021-04-27|website=Arm Developer|language=en}}</ref> from [[Arm Ltd.|ARM Ltd]], which belongs to AMBA5 group of specifications defines the interfaces for the connection of fully coherent processors.