Editing CMOS (section)

=== Logic ===
[[File:CMOS NAND.svg|thumb|upright|[[NAND gate]] in CMOS logic]]

More complex logic functions such as those involving [[AND gate|AND]] and [[OR gate]]s require manipulating the paths between gates to represent the logic. When a path consists of two transistors in series, both transistors must have low resistance to the corresponding supply voltage, modelling an AND. When a path consists of two transistors in parallel, either one or both of the transistors must have low resistance to connect the supply voltage to the output, modelling an OR.

Shown on the right is a [[circuit diagram]] of a [[NAND gate]] in CMOS logic. If both of the A and B inputs are high, then both the NMOS transistors (bottom half of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive path will be established between the output and ''V''<sub>ss</sub> (ground), bringing the output low. If both of the A and B inputs are low, then neither of the NMOS transistors will conduct, while both of the PMOS transistors will conduct, establishing a conductive path between the output and ''V''<sub>dd</sub> (voltage source), bringing the output high.  If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive path will be established between the output and ''V''<sub>dd</sub> (voltage source), bringing the output high.  As the only configuration of the two inputs that results in a low output is when both are high, this circuit implements a [[NAND gate|NAND]] (NOT AND) logic gate.

An advantage of CMOS over NMOS logic is that both low-to-high and high-to-low output transitions are fast since the (PMOS) pull-up transistors have low resistance when switched on, unlike the load resistors in NMOS logic. In addition, the output signal swings the full [[voltage]] between the low and high rails. This strong, more nearly symmetric response also makes CMOS more resistant to noise.

See [[Logical effort]] for a method of calculating delay in a CMOS circuit.