Editing CDC 6600 (section)

==={{anchor|60-bit floating point}}Central Processor (CP)===
{| class="infobox" style="font-size:88%;width:32em;"
|-
|+ CDC 6x00 registers
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>5</sup><sub>9</sub>
| style="width:160px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:70px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:auto;" | ''(bit position)''
|- 
|colspan="6" | '''Operand registers''' ''(60 bits)''
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X0
| style="width:auto; background:white; color:black;"| Register 0
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X1 (read)
| style="width:auto; background:white; color:black;"| Register 1
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X2 (read)
| style="width:auto; background:white; color:black;"| Register 2
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X3 (read)
| style="width:auto; background:white; color:black;"| Register 3
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X4 (read)
| style="width:auto; background:white; color:black;"| Register 4
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X5 (read)
| style="width:auto; background:white; color:black;"| Register 5
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X6 (write)
| style="width:auto; background:white; color:black;"| Register 6
|- style="background:silver;color:black"
| style="text-align:center" colspan="5"| X7 (write)
| style="width:auto; background:white; color:black;"| Register 7
|- 
|colspan="6" | '''Address registers''' ''(18 bits)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A0
| style="width:auto; background:white; color:black;"| Address 0
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A1 (read address)
| style="width:auto; background:white; color:black;"| Address 1
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A2 (read address)
| style="width:auto; background:white; color:black;"| Address 2
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A3 (read address)
| style="width:auto; background:white; color:black;"| Address 3
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A4 (read address)
| style="width:auto; background:white; color:black;"| Address 4
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A5 (read address)
| style="width:auto; background:white; color:black;"| Address 5
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A6 (write address)
| style="width:auto; background:white; color:black;"| Address 6
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| A7 (write address)
| style="width:auto; background:white; color:black;"| Address 7
|- 
|colspan="6" | '''Increment registers''' ''(18 bits)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B0 ''(all bits zero)''
| style="width:auto; background:white; color:black;"| Increment 0
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B1
| style="width:auto; background:white; color:black;"| Increment 1
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B2
| style="width:auto; background:white; color:black;"| Increment 2
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B3
| style="width:auto; background:white; color:black;"| Increment 3
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B4
| style="width:auto; background:white; color:black;"| Increment 4
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B5
| style="width:auto; background:white; color:black;"| Increment 5
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B6
| style="width:auto; background:white; color:black;"| Increment 6
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| B7
| style="width:auto; background:white; color:black;"| Increment 7
|- 
|colspan="6" | '''Program address''' ''(18 bits)''
|- style="background:silver;color:black"
| style="text-align:center;background:#FFF" colspan="2"| &nbsp;
| style="text-align:center" colspan="3"| P
|}
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The Central Processor (CP) and main memory of the 6400, 6500, and 6600 machines had a 60-bit word length. The Central Processor had eight general purpose [[60-bit computing|60-bit]] [[processor register|registers]] X0 through X7, eight [[18-bit computing|18-bit]] address registers A0 through A7, and eight 18-bit "increment" registers B0 through B7. B0 was held at zero permanently by the hardware. Many programmers found it useful to set B1 to 1, and similarly treat it as inviolate.

The CP had no instructions for input and output, which are accomplished through Peripheral Processors (below). No opcodes were specifically dedicated to loading or storing memory; this occurred as a side effect of assignment to certain A registers. Setting A1 through A5 loaded the word at that address into X1 through X5 respectively; setting A6 or A7 stored a word from X6 or X7. No side effects were associated with A0. A separate hardware load/store unit, called the ''stunt box'', handled the actual data movement independently of the operation of the instruction stream, allowing other operations to complete while memory was being accessed, which required eight cycles, in the best case.

The 6600 CP included ten parallel functional units, allowing multiple instructions to be worked on at the same time. Today,{{Clarify timeframe|date=May 2022}} this is known as a [[superscalar processor]] design, but it was unique for its time. Unlike most modern CPU designs, functional units were not pipelined; the functional unit would become busy when an instruction was "issued" to it and would remain busy for the entire time required to execute that instruction. (By contrast, the CDC 7600 introduced pipelining into its functional units.) In the best case, an instruction could be issued to a functional unit every 100&nbsp;ns clock cycle. The system read and decoded instructions from memory as fast as possible, generally faster than they could be completed, and fed them off to the units for processing. The units were:
* floating point multiply (two copies)
* floating point divide
* floating point add
* "long" integer add
* incrementers (two copies; performed memory load/store)
* shift
* Boolean logic
* branch

Floating-point operations were given pride of place in this [[Computer architecture|architecture]]: the CDC 6600 (and kin) stand virtually alone in being able to execute a 60-bit [[Floating-point arithmetic|floating point]] multiplication in time comparable to that for a program branch.
A recent analysis by Mitch Alsup of James Thornton's book, "Design of a Computer",
revealed that the 6600's Floating Point unit is a 2 stage pipelined design.

Fixed point addition and subtraction of 60-bit numbers were handled in the Long Add Unit, using [[ones' complement]] for negative numbers. Fixed point multiply was done as a special case in the floating-point multiply unit—if the exponent was zero, the FP unit would do a single-precision 48-bit floating-point multiply and clear the high exponent part, resulting in a 48-bit integer result. Integer divide was performed by a macro, converting to and from floating point.<ref>{{Cite web |url=http://ed-thelen.org/comp-hist/CDC-6600-R-M.html#P3-21 |title=Archived copy |access-date=2005-06-13 |archive-url=https://web.archive.org/web/20140102194752/http://ed-thelen.org/comp-hist/CDC-6600-R-M.html#P3-21 |archive-date=2014-01-02 |url-status=dead }}</ref>

Previously executed instructions were saved in an eight-word [[CPU cache|cache]], called the "stack". In-stack jumps were quicker than out-of-stack jumps because no memory fetch was required. The stack was flushed by an unconditional jump instruction, so unconditional jumps at the ends of loops were conventionally written as conditional jumps that would always succeed.

The system used a 10&nbsp;[[Hertz|MHz]] clock, with a [[clock signal#4-phase clock|four-phase signal]]. A floating-point multiplication took ten cycles, a division took 29, and the overall performance, taking into account memory delays and other issues, was about 3&nbsp;[[FLOPS|MFLOPS]]. Using the best available compilers, late in the machine's history, [[Fortran|FORTRAN]] programs could expect to maintain about 0.5&nbsp;MFLOPS.