Editing Athlon (section)

===Athlon Classic (1999)===
{{Infobox CPU
| name = Athlon Classic
| image = AMD-Athlon-Processor-Logo.svg
| caption = The logo of the Athlon "Classic"
| produced-start = June 23, 1999
| produced-end = 
| slowest = 500 | slow-unit = MHz
| fastest = 1400 | fast-unit = MHz
| fsb-slowest = 100 | fsb-slow-unit = Mhz
| fsb-fastest = 133 | fsb-fast-unit = Mhz
| size-from = 250 nm
| size-to = 180 nm
| manuf1 = AMD    
| core1 = Argon (K7)
| core2 = Pluto/Orion (K75)
| core3 = Thunderbird
| predecessor = [[AMD K6-III|K6-III]]
| successor = [[Athlon XP]]
| sock1 = [[Slot A]]
| sock2 = [[Socket A]]
| sock3 = [[Socket 563]]
| arch = [[x86]]
}}

The AMD Athlon processor launched on June 23, 1999, with general availability by August 1999. Subsequently, from August 1999 until January 2002, this initial K7 processor was the fastest x86 chip in the world.<ref name="A">{{Cite web |url=http://www.cpu-collection.de/?l0=co&l1=amd&l2=athlon |title=amd athlon |website=cpu-collection.de |access-date=2017-02-24}}</ref> At launch it was, on average, 10% faster than the Pentium&nbsp;III at the same clock for business applications and 20% faster for gaming workloads.<ref name="Shimpy for AnadTech: 1999">{{citation |author=Lal Shimpi, Anand |url=http://www.anandtech.com/show/355/3 |title=AMD Athlon |date=August 9, 1999 |access-date=January 6, 2012 |quote=The performance of the K7, then clocked at 500&nbsp;MHz, was on par with a Pentium&nbsp;III&nbsp;500.}}</ref> In commercial terms, the Athlon "Classic" was an enormous success.<ref name="Anandtech Heaven: 2001"/>

;Features
[[Image:Amd athlon classic.jpg|left|thumb|Logo on Slot A Athlon cartridge]]

The Athlon Classic is a cartridge-based processor, named [[Slot&nbsp;A]] and similar to Intel's cartridge [[Slot&nbsp;1]] used for Pentium&nbsp;II and Pentium&nbsp;III. It used the same, commonly available, physical 242-pin connector used by Intel Slot&nbsp;1 processors but rotated by 180&nbsp;degrees to connect the processor to the [[motherboard]]. The cartridge assembly allowed the use of higher-speed cache memory modules than could be put on (or reasonably bundled with) motherboards at the time. Similar to the Pentium&nbsp;II and the Katmai-based Pentium&nbsp;III, the Athlon Classic contained 512&nbsp;KB of L2 cache. This high-speed [[Static random-access memory|SRAM]] cache was run at a divisor of the processor clock and was accessed via its own 64-bit [[back-side bus]], allowing the processor to service both [[front-side bus]] requests and cache accesses simultaneously, as compared to pushing everything through the front-side bus.<ref name="Aces Hrdware by Gels: 1999">{{citation |author=De Gelas, Johan |url=http://aceshardware.com/read.jsp?id=71|archive-url=https://web.archive.org/web/20011225163156/http://aceshardware.com/read.jsp?id=71 |title=Clash of Silicon, The Athlon 650 |publisher=Ace's Hardware |date=September 29, 1999 |archive-date=December 25, 2001 |access-date=January 6, 2012}}.</ref>

The Argon-based Athlon contained 22 million transistors and measured 184&nbsp;mm<sup>2</sup>. It was fabricated by AMD in a version of their CS44E process, a 250&nbsp;nm [[complementary metal–oxide–semiconductor]] (CMOS) process with six levels of [[aluminium interconnect]].<ref name="JSSC-1999-11-11">{{citation |author=Golden, Michael |year=1999 |title=A Seventh-Generation x86 Microprocessor |journal=[[IEEE Journal of Solid-State Circuits]] |volume=34 |issue=11 |pages=1466–1477 |doi=10.1109/4.799851|bibcode=1999IJSSC..34.1466G |display-authors=etal}}.</ref><ref name="MPR-1998-10-26">{{citation |author=Keith Diefendorff|author-link=Keith Diefendorff |title=K7 Challenges Intel |journal=[[Microprocessor Report]] |date=October 26, 1998 |volume=12 |issue=14 |url=http://www3.hi.is/~hh/kennsla/ht/Athlon.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www3.hi.is/~hh/kennsla/ht/Athlon.pdf |archive-date=2022-10-09 |url-status=live |access-date=January 6, 2012}}.</ref> "Pluto" and "Orion" Athlons were fabricated in a 180&nbsp;nm process.<ref name="PC Hardware in a Nuthshell"/>

[[Image:Athlon arch.png|thumb|left|350px|Athlon architecture]]
[[Image:Slot-A Athlon.jpg|thumb|250px|An open Slot A cartridge. MPU die is in the center.]]
[[Image:Argonathlon.jpg|thumb|250px|Athlon Slot A cartridge. Note heat sink and cooling fan assembly on rear side.]]
The Athlon's [[CPU cache]] consisted of the typical two levels. Athlon was the first x86 processor with a 128&nbsp;[[kilobyte|KB]]<ref>{{BDprefix|p=b}}</ref> split level-1 cache; a [[CPU cache|2-way associative]] cache separated into 2×64&nbsp;KB for data and instructions (a concept from [[Harvard architecture]]).<ref name=PaulHsieh /> SRAM cache designs at the time were incapable of keeping up with the Athlon's clock scalability, resulting in compromised CPU performance in some computers.<ref name="Anandtech again: 2000">{{citation |author=Lal Shimpi, Anand |url=http://www.anandtech.com/showdoc.aspx?i=1189&p=2|title=AMD Athlon 1&nbsp;GHz, 950&nbsp;MHz, 900&nbsp;MHz |publisher=Anandtech |page=2 |date=March 6, 2000}}.</ref> With later Athlon models, AMD would integrate the L2 cache onto the processor itself, removing dependence on external cache chips.<ref name="PC Hardware in a Nuthshell">{{cite news |author=Robert Bruce Thompson, Barbara Fritchman |title=PC Hardware in a Nutshell: A Desktop Quick Reference|url=https://books.google.com/books?id=kG8LcWfruOAC&q=thoroughbred+A+die+shrink+palomino&pg=PT64 |work=Thompson |date=July 24, 2003 |isbn=9780596552343|access-date=August 4, 2020}}</ref> The Slot-A Athlons were the first multiplier-locked CPUs from AMD, preventing users from setting their own desired clock speed. This was done by AMD in part to hinder CPU remarking and overclocking by resellers, which could result in inconsistent performance. Eventually a product called the "Goldfingers device" was created that could unlock the CPU.<ref name="Overclockers: 2000">{{citation |author=Jim Noonan; James Rolfe |url=http://www.overclockers.com.au/techstuff/r_gfd1/ |title=Athlon Gold-Finger Devices |publisher=Overclockers.com.au |date=March 21, 2000 |archive-url=https://web.archive.org/web/20090201190219/http://www.overclockers.com.au/techstuff/r_gfd1/ |archive-date=February 1, 2009 |access-date=January 6, 2012}}.</ref>

AMD designed the CPU with more robust x86 instruction decoding capabilities than that of K6, to enhance its ability to keep more data in-flight at once.<ref name=PaulHsieh>{{citation |author=Paul Hsieh |url=http://www.azillionmonkeys.com/qed/cpujihad.shtml|title=7th Generation CPU Comparisons |date=August 11, 1999 |access-date=January 6, 2012}}.</ref> The critical branch-predictor unit was enhanced compared to the K6. Deeper pipelining with more stages allowed higher clock speeds to be attained.<ref name="De Gelas: 2001">De Gelas, Johan. [https://web.archive.org/web/20011124231810/http://www.aceshardware.com/Spades/read.php?article_id=50 The Secrets of High Performance CPUs, Part 1], Ace's Hardware, September 29, 1999.</ref> Like the AMD K5 and K6, the Athlon dynamically buffered internal micro-instructions at runtime resulting from parallel x86 instruction decoding. The CPU is an [[Out-of-order execution|out-of-order]] design, again like previous post-5x86 AMD CPUs. The Athlon utilizes the [[Alpha 21264]]'s EV6 bus architecture with [[double data rate]] (DDR) technology.{{citation needed|date=August 2020}}

AMD ended its long-time handicap with [[floating point]] [[x87]] performance by designing a super-[[Pipeline (computing)|pipelined]], out-of-order, triple-issue [[floating-point unit]] (FPU).<ref name=PaulHsieh /> Each of its three units could independently calculate an optimal type of instructions with some redundancy, making it possible to operate on more than one floating-point instruction at once.<ref name=PaulHsieh /> This FPU was a huge step forward for AMD, helping compete with Intel's [[P6 (microarchitecture)|P6]] FPU.<ref name="Pabst for Toms: 1999">{{citation |author=Pabst, Thomas |url=http://www.tomshardware.com/reviews/performance,124-7.html|title=Performance-Showdown between Athlon and Pentium III |publisher=Tom's Hardware |date=August 23, 1999 |access-date=January 6, 2012}}.</ref> The [[3DNow!]] floating-point [[Single instruction, multiple data|SIMD]] technology, again present, received some revisions and was renamed "Enhanced 3DNow!" Additions included [[digital signal processing|DSP]] instructions and the [[extended MMX]] subset of [[Streaming SIMD Extensions|Intel&nbsp;SSE]].<ref name="Womack for Womack: 2012">{{citation |author=Womack, Tom |url=http://www.tom.womack.net/x86FAQ/faq_features.html |title=Extensions to the x86 architecture |access-date=January 6, 2012 |archive-url=https://web.archive.org/web/20120115195956/http://www.tom.womack.net/x86FAQ/faq_features.html |archive-date=January 15, 2012 |url-status=dead |df=mdy-all }}.</ref>

;Specifications
* L1-cache: 64 + 64&nbsp;KB (data + instructions)
* L2-cache: 512&nbsp;KB, external chips on CPU module with 50%, 40% or 33% of CPU speed
* [[MMX (instruction set)|MMX]], [[3DNow!]]
* [[Slot A]] (EV6)
* [[Front-side bus]]:100&nbsp;MHz (200MT/s)
* Vcore: 1.6&nbsp;V (K7), 1.6–1.8&nbsp;V (K75)
* First release: June 23, 1999 (K7), November 29, 1999 (K75)
* Clock-rate: 500–700&nbsp;MHz (K7), 550–1000&nbsp;MHz (K75)