Editing Zilog Z80 (section)

=== Comparison with the 8080 ===
Faggin designed the [[instruction set]] to be [[binary-code compatibility|binary compatible]] with the 8080{{sfnp|Anderson|1994|p=57}}<ref name="Brock 2003">{{Cite book |last=Brock |first=Gerald W. |url=https://archive.org/details/secondinformatio0000broc |title=The second information revolution |date=2003 |publisher=Harvard University Press |isbn=978-0-674-01178-6 |url-access=registration}}</ref> so that most 8080 code, notably the [[CP/M]] [[operating system]] and Intel's [[PL/M]] compiler for 8080 (as well as its generated code), would run unmodified on the new Z80 CPU. Masatoshi Shima designed most of the [[microarchitecture]] as well as the gate and transistor levels of the Z80 CPU, assisted by a small number of engineers and [[integrated circuit layout|layout]] people.<ref>{{Cite magazine |date=November 29, 1982 |title=History of the 8-bit: travelling far in a short time |url=https://books.google.com/books?id=HjAEAAAAMBAJ&pg=PA58 |url-status=live |archive-url=https://web.archive.org/web/20240105080752/https://books.google.com/books?id=HjAEAAAAMBAJ&pg=PA58 |archive-date=January 5, 2024 |magazine=[[InfoWorld]] |publisher=Popular Computing Inc. |location=Palo Alto, CA |pages=58–60 |volume=4 |issue=47 |issn=0199-6649}}</ref><ref>{{Cite magazine |last1=Faggin |first1=Federico |last2=Shima |first2=Masatoshi |author-link2=Masatoshi Shima |last3=Ungermann |first3=Ralph |date=August 19, 1976 |title=Z-80 chip set heralds third microprocessor generation |url=https://www.worldradiohistory.com/Archive-Electronics/70s/76/Electronics-1976-08-19.pdf#page=91 |url-status=live |archive-url=https://web.archive.org/web/20230131151012/https://worldradiohistory.com/Archive-Electronics/70s/76/Electronics-1976-08-19.pdf#page=91 |archive-date=January 31, 2023 |magazine=[[Electronics (magazine)|Electronics]] |publisher=[[McGraw Hill Education|McGraw–Hill]] |location=New York |pages=89–93 |volume=49 |issue=17}}</ref> CEO Federico Faggin was actually heavily involved in the chip layout work, together with two dedicated layout people. According to Faggin, he worked 80&nbsp;hours a week in order to meet the tight schedule given by the financial investors.{{sfn|Faggin|Shima|Ungermann|2007}}

The Z80 offered multiple improvements over the 8080:<ref name="Brock 2003" />
* An enhanced [[instruction set]] including:
** a more logical, comprehensible and readable system of assembler instruction [[Assembly language#Opcode mnemonics and extended mnemonics|mnemonics]]
** more flexible 16-bit data movement (load, or LD) instructions, crucially including the stack pointer SP
** more flexible addressing modes for input/output to external peripheral ports
** single-bit addressing of all registers and memory, including bit testing
** shifts/rotates on memory and registers other than the [[accumulator (computing)|accumulator]]
** improved and more accurate (than the previous 8080) [[binary-coded decimal|BCD]] arithmetic
** rotate instructions for BCD number strings in memory
** 16-bit subtraction and 8-bit negation
** [[program loop]]ing
** program counter (PC) relative jumps
** [[block move|block copy]], block [[input/output]] (I/O), and byte search instructions.{{sfnp|Ciarcia|1981|pp=31, 32}}
* An [[overflow flag]] with better support for signed 8- and 16-bit arithmetics.{{efn|Although the 8080 had 16-bit addition and 16-bit [[Increment and decrement operators|increment and decrement instructions]], it had no explicit 16-bit subtraction, and no overflow flag. The Z80 complemented this with the ADC&nbsp;HL,rr and SBC&nbsp;HL,rr instructions, which sets the new overflow flag accordingly. (The 8080-compatible ADD&nbsp;HL,rr does not.)}}
* New IX and IY [[index register]]s with instructions for direct ''base+[[Offset (computer science)|offset]]'' addressing
* A better [[interrupt]] system:
** A more automatic and general [[Interrupt vector|vectorized interrupt system]], ''mode&nbsp;2'', primarily intended for Zilog's line of counter/timers, DMA and communications controllers, as well as a fixed vector interrupt system, ''mode&nbsp;1'', for simple systems with minimal hardware (with ''mode&nbsp;0'' being the 8080-compatible mode).<ref name="Wai-Kai 2002">{{Cite book |last=Chen |first=Wai-Kai |title=The circuits and filters handbook |date=2002 |publisher=[[CRC Press]] |isbn=978-0-8493-0912-0 |page=1943 |quote=interrupt processing commences according to the interrupt method stipulated by the IM&nbsp;''i'', ''i''&nbsp;= 0, 1, or 2, instruction. If ''i''&nbsp;= 1, for direct method, the PC is loaded with 0038H. If ''i''&nbsp;= 0, for vectored method, the interrupting device has the opportunity to place the op-code for one byte. If ''i''&nbsp;= 2, for indirect vector method, the interrupting device must then place a byte. The Z80 then uses this byte where one of 128 interrupt vectors can be selected by the byte.}}</ref>
** A non-maskable interrupt (NMI), which can be used to respond to power-down situations or other high-priority events (and allowing a minimalistic Z80 system to easily implement a two-level interrupt scheme in ''mode&nbsp;1'').
* A complete duplicate [[register file]],<ref>{{Cite book |last=Mathur |title=Introduction to Microprocessors |date=1989 |publisher=Tata McGraw-Hill Publishing Company |isbn=978-0-07-460222-5 |page=111 |quote=The register architecture of the Z80 is more innovative than that of the 8085}}</ref> which could be quickly switched, to speed up response to [[interrupt]]s such as fast asynchronous event handlers or a [[multitasking (computing)|multitasking]] [[scheduler (computing)|dispatcher]]. Although they were not intended as extra registers for general code, they were nevertheless used that way in some applications.{{efn|Notably to simultaneously handle the 32-bit [[significand|mantissas]] of two [[operand]]s in the 40-bit [[floating-point arithmetic|floating-point]] format used in the [[ZX81]] home computer. They were also used in a similar fashion in some earlier but lesser known Z80-based computers, such as the Swedish [[ABC&nbsp;80]] and [[ABC&nbsp;800]].}}
* Less hardware required for [[power supply]], clock generation and interface to memory and I/O
* Single 5-volt power supply (the 8080 needed −5&nbsp;V, +5&nbsp;V, and +12&nbsp;V).
* Single-phase 5-volt clock (the 8080 needed a high-amplitude (9 to 12&nbsp;volts) non-overlapping [[two-phase clock]]).
* Built-in [[DRAM]] [[memory refresh|refresh]], which would otherwise require external circuitry, unless SRAM, more expensive and less dense (but faster), was used.{{efn|As this refresh does not need to transfer any data, just output sequential row-addresses, it occupies less than 1.5 T-states. The dedicated M1-signal (''machine cycle one'') in the Z80 can be used to allow memory chips the same amount of access time for instruction fetches as for data access, i.e almost 2 full T-states out of the 4T ''fetch'' cycle (as well as out of the 3T data ''read'' cycle). The Z80 could use memory with the same range of access times as the 8080 (or the 8086) at the same clock frequency. This long M1-signal (relative to the clock) also meant that the Z80 could employ about 4–5 times the internal frequency of a 6800, 6502 or similar using the same type of memory.}}
* Non-multiplexed buses (the 8080 had state signals multiplexed onto the data bus).
* A special reset that zeroes only the program counter, so that a single Z80 CPU could be used in a development system such as an [[in-circuit emulator]].<ref>{{Cite web |last=Brewer |first=Tony |title=Z80 Special Reset |website=[[GitHub]] |url=https://github.com/redcode/Z80/wiki/Z80-Special-Reset |access-date=April 27, 2024 |archive-date=April 27, 2024 |archive-url=https://web.archive.org/web/20240427180745/https://github.com/redcode/Z80/wiki/Z80-Special-Reset |url-status=live }}</ref>