Editing Wafer (electronics) (section)

== Wafer properties ==

=== Standard wafer sizes ===
==== Silicon substrate ====
Silicon wafers are available in a variety of diameters from 25.4&nbsp;mm (1&nbsp;inch) to 300&nbsp;mm (11.8&nbsp;inches).<ref name=f450c>{{cite web|title = Evolution Of Silicon Wafer {{!}} F450C|url = http://www.f450c.org/infographic/|archive-url = https://archive.today/20160105165200/http://www.f450c.org/infographic/|url-status = usurped|archive-date = January 5, 2016|website = F450C|access-date = 2015-12-17|language = en-US}}</ref><ref>{{cite web |title=Silicon Wafer |url=http://www.semiwafer.com/products/silicon.htm |access-date=2008-02-23  |archive-url=https://web.archive.org/web/20080220102757/http://www.semiwafer.com/products/silicon.htm |archive-date=2008-02-20 }}</ref> [[Semiconductor fabrication plant]]s, colloquially known as ''fabs'', are defined by the diameter of wafers that they are tooled to produce. The diameter has gradually increased to improve throughput and reduce cost with the current state-of-the-art fab using {{nowrap|300 mm}}, with a proposal to adopt {{nowrap|450 mm}}.<ref>{{cite web|url=http://www.intel.com/pressroom/archive/releases/20080505corp.htm|title=Intel, Samsung, TSMC reach agreement about 450mm tech|website=intel.com}}</ref><ref>[http://www.itrs.net/Links/2008Summer/Public Presentations/PDF/FEP.pdf ITRS Presentation (PDF)]{{Dead link|date=August 2018 |bot=InternetArchiveBot |fix-attempted=yes }}</ref> [[Intel]], [[TSMC]], and [[Samsung]] were separately conducting research to the advent of {{nowrap|450 mm}} "[[prototype]]" (research) [[fab (semiconductors)|fab]]s, though serious hurdles remain.<ref>{{cite web |url=https://www.eetimes.com/450-mm-fab-debate-surfaces/ |title=450-mm fab debate surfaces |last=LaPedus |first=Mark |date=January 14, 2009 |website=EE Times |publisher=Aspencore |access-date=2021-05-09 |quote=As reported, Intel, TSMC and Samsung are separately pushing for the advent of 450-mm ''prototype'' fabs by 2012}}</ref>

[[File:Wafer 2 Zoll bis 8 Zoll 2.jpg|thumb|275px|{{convert|2|in|mm|adj=on}}, {{convert|4|in|mm|adj=on}}, {{convert|6|in|mm|adj=on}}, and {{convert|8|in|mm|adj=on}} wafers]]
{| class="wikitable sortable mw-collapsible" style="text-align:center"
|-
! Wafer size
! Typical thickness
! Year introduced <ref name=f450c />
! Weight per wafer
! 100&nbsp;mm<sup>2</sup> die per wafer
|-
| {{convert|1|in|mm|adj=on}}
|
| 1960
|
|
|-
| {{convert|2|in|mm|adj=on}}
| 275 [[μm]]
| 1969
|
|9
|-
| {{convert|3|in|mm|adj=on}}
| 375&nbsp;μm
| 1972
|
|29
|-
| {{convert|4|in|mm|adj=on}}
| 525&nbsp;μm
| 1976
| 10 grams <ref name="auto">{{cite web|url=http://wafercare.com/Page.aspx?id=1012|archive-url=https://web.archive.org/web/20131207002716/http://wafercare.com/Page.aspx?id=1012|archive-date=December 7, 2013|title=450 mm Wafer Handling Systems|date=December 7, 2013}}</ref>
| 56
|-
| 4.9&nbsp;inch (125&nbsp;mm)
| 625&nbsp;μm
| 1981
|
|95
|-
| 150&nbsp;mm (5.9&nbsp;inch, usually referred to as "6 inch")
| 675&nbsp;μm
| 1983
|
|144
|-
| 200&nbsp;mm (7.9&nbsp;inch, usually referred to as "8 inch")
| 725&nbsp;μm.
| 1992
| 53 grams <ref name="auto"/>
| 269
|-
| 300&nbsp;mm (11.8&nbsp;inch, usually referred to as "12 inch")
| 775&nbsp;μm
| 1999
| 125 grams<ref name="auto"/>
| 640
|-
| {{nowrap|450 mm}} (17.7&nbsp;inch) (proposed)<ref>{{cite web|url=https://www.eetimes.com/document.asp?doc_id=1169573|title=Industry agrees on first 450-mm wafer standard|first=Mark|last=LaPedus|website=EETimes}}</ref> 
| 925&nbsp;μm
| –
| 342 grams <ref name="auto"/>
| 1490
|-
| {{convert|675|mm|in|adj=on}} (theoretical)<ref>{{cite web|url=https://www.daifuku.com/solution/technology/semiconductor/|title=The Evolution of AMHS|website=www.daifuku.com|access-date=2018-12-02|archive-date=2019-04-08|archive-url=https://web.archive.org/web/20190408010203/https://www.daifuku.com/solution/technology/semiconductor/}}</ref>
| unknown
| –
| unknown
| 3427
|}
Wafers grown using materials other than silicon will have different thicknesses than a silicon wafer of the same diameter. Wafer thickness is determined by the [[mechanical strength]] of the material used; the wafer must be thick enough to support its own weight without cracking during handling. The tabulated thicknesses relate to when that process was introduced, and are not necessarily correct currently, for example the IBM BiCMOS7WL process is on 8-inch wafers, but these are only 200&nbsp;μm thick. The weight of the wafer increases with its thickness and the square of its diameter.  Date of introduction does not indicate that factories will convert their equipment immediately, in fact, many factories do not bother upgrading.  Instead, companies tend to expand and build whole new lines with newer technologies, leaving a large spectrum of technologies in use at the same time.

==== Gallium Nitride substrate ====
GaN substrate wafers typically have had their own independent timelines, parallel but far lagging silicon substrate, but ahead of other substrates.  The world's first 300 mm wafer made of GaN was announced in Sept 2024 by Infineon, suggesting in the coming future they could put into use the first factory with 300 mm GaN commercial output.<ref>https://asia.nikkei.com/Business/Tech/Semiconductors/Infineon-unveils-world-s-first-12-inch-GaN-power-chip-wafer-tech</ref>

==== SiC substrate ====
Meanwhile world's first Silicon Carbide (SiC) 200 mm wafers were announced in July 2021 by ST Microelectronics.<ref>https://newsroom.st.com/media-center/press-item.html/t4380.html</ref> It is not known if SiC 200 mm has entered volume production as of 2024, as typically the largest fabs for SiC in commercial production remain at 150 mm.

==== Silicon on sapphire ====
[[Silicon on sapphire]] is different from silicon substrate as the substrate is sapphire, while superstrate is silicon, while epitaxal layers and doping can be anything. SOS in commercial production is typically maxed out at 150 mm wafer sizes as of 2024.

==== Gallium Arsenide substrate ====
GaAs wafers tend to be 150 mm at largest, in commercial production as of 2024.<ref>https://www.3dincites.com/2024/04/the-role-of-200mm-manufacturing-in-enabling-a-1-trillion-semiconductor-industry/</ref>

==== Aluminum Nitride substrate ====
AlN tends to be 50 mm or 2 inch wafers in commercial production, while 100 mm or 4 inch wafers are [https://www.asahi-kasei.com/news/2024/e240612.html being developed as of 2024] by wafer suppliers like Asahi Kasei.  However, merely because a wafer exists commercially, does not imply in any way that processing equipment to produce chips on that wafer exists, indeed such equipment tends to lag development until paying end customer demand materializes.  Even after equipment is developed (years), it can take further years for fabs to figure out how to use the machines productively.

==== Historical increases of wafer size ====
A unit of [[wafer fabrication]] step, such as an etch step, can produce more chips proportional to the increase in wafer area, while the cost of the unit fabrication step goes up more slowly than the wafer area. This was the cost basis for increasing wafer size. Conversion to 300&nbsp;mm wafers from 200&nbsp;mm wafers began in early 2000, and reduced the price per die for about 30–40%.{{cn|date=December 2024}}Larger diameter wafers allow for more die per wafer.

==== Photovoltaic ====
{{expand section|date=July 2020}}
M1 wafer size (156.75&nbsp;mm) is in the process of being phased out in China as of 2020. Various nonstandard wafer sizes have arisen, so efforts to fully adopt the M10 standard (182&nbsp;mm) are ongoing. Like other semiconductor fabrication processes, driving down costs has been the main driving factor for this attempted size increase, in spite of the differences in the manufacturing processes of different types of devices.{{Citation needed|date=February 2022}}

=== Crystalline orientation ===
[[File:Silicon-unit-cell-3D-balls.png|thumb|Diamond cubic crystal structure of a silicon unit cell]]
[[File:Wafer flats convention v2.svg|thumb|Flats can be used to denote [[doping (semiconductors)|doping]] and [[crystallography|crystallographic]] orientation. Red represents material that has been removed.]]

Wafers are grown from crystal having a regular [[crystal structure]], with silicon having a [[diamond cubic]] structure with a lattice spacing of 5.430710 Å (0.5430710&nbsp;nm).<ref name="HandbookSi">{{cite book|last=O'Mara|first=William C.|url=https://books.google.com/books?id=COcVgAtqeKkC&q=Czochralski+Silicon+Crystal+Face+Cubic&pg=PA351|title=Handbook of Semiconductor Silicon Technology|publisher=William Andrew Inc.|year=1990|isbn=978-0-8155-1237-0|pages=349–352|access-date=2008-02-24}}</ref> When cut into wafers, the surface is aligned in one of several relative directions known as crystal orientations. Orientation is defined by the [[Miller index]] with (100) or (111) faces being the most common for silicon.<ref name=HandbookSi/>
Orientation is important since many of a single crystal's structural and electronic properties are highly [[anisotropic]]. [[Ion implantation]] depths depend on the wafer's crystal orientation, since each direction offers distinct [[Ion implantation#Ion channelling|paths]] for transport.<ref>{{cite book|last=Nishi|first=Yoshio|url=https://books.google.com/books?id=Qi98H-iTgLEC&q=wafer+flat+and+notch&pg=PA70|title=Handbook of Semiconductor Manufacturing Technology|publisher=CRC Press|location=Boca Raton, Florida|year=2000|isbn=978-0-8247-8783-7|pages=108–109|access-date=2008-02-25}}</ref>

Wafer [[cleavage (crystal)|cleavage]] typically occurs only in a few well-defined directions. Scoring the wafer along cleavage planes allows it to be easily diced into individual chips ("[[Die (integrated circuit)|die]]s") so that the billions of individual [[Electronic component|circuit elements]] on an average wafer can be separated into many individual circuits.{{Citation needed|date=February 2021}}

=== Crystallographic orientation notches ===

Wafers under 200&nbsp;mm diameter have ''flats'' cut into one or more sides indicating the [[crystallography|crystallographic]] planes of the wafer (usually a {110} face). In earlier-generation wafers a pair of flats at different angles additionally conveyed the doping type (see illustration for conventions). Wafers of 200&nbsp;mm diameter and above use a single small notch to convey wafer orientation, with no visual indication of doping type. 450 mm wafers are notchless, relying on a laser scribed structure on the wafer surface for orientation.<ref>{{cite web|last=Föll|first=Helmut|date=October 2019|title=Wafer Flats|url=http://www.tf.uni-kiel.de/matwis/amat/elmat_en/kap_5/illustr/i5_2_4.html|access-date=2008-02-23|publisher=[[University of Kiel]]}}</ref>

=== Impurity doping ===

Silicon wafers are generally not 100% pure silicon, but are instead formed with an initial impurity [[Doping (semiconductors)|doping]] concentration between 10<sup>13</sup> and 10<sup>16</sup> atoms per cm<sup>3</sup> of [[boron]], [[phosphorus]], [[arsenic]], or [[antimony]] which is added to the melt and defines the wafer as either bulk n-type or p-type.<ref>{{cite book|last=Widmann|first=Dietrich|url=https://books.google.com/books?id=uYNn1N6YSwQC&q=Czochralski+Doping+Silicon&pg=PA39|title=Technology of Integrated Circuits|publisher=Springer|year=2000|isbn=978-3-540-66199-3|page=39|access-date=2008-02-24}}</ref> However, compared with single-crystal silicon's atomic density of 5×10<sup>22</sup> atoms per cm<sup>3</sup>, this still gives a purity greater than 99.9999%. The wafers can also be initially provided with some [[interstitial defect|interstitial]] oxygen concentration. Carbon and metallic contamination are kept to a minimum.<ref>{{cite book|last=Levy|first=Roland Albert|url=https://books.google.com/books?id=wZPRPU6ne7UC&pg=PA248|title=Microelectronic Materials and Processes|year=1989|isbn=978-0-7923-0154-7|pages=6–7, 13|publisher=Springer |access-date=2008-02-23}}</ref> [[Transition metal]]s, in particular, must be kept below parts per billion concentrations for electronic applications.<ref>{{cite book|last=Rockett|first=Angus|title=The Materials Science of Semiconductors|year=2008|isbn=978-0-387-25653-5|page=13|publisher=Springer }}</ref>