Editing Transistor–transistor logic (section)

=== TTL with a "totem-pole" output stage ===
[[File:7400 Circuit.svg|thumb|Standard TTL NAND with a "totem-pole" output stage, one of four in 7400]]

To solve the problem with the high output resistance of the simple output stage the second schematic adds to this a "totem-pole" ("[[push–pull output|push–pull]]") output. It consists of the two n-p-n transistors V<sub>3</sub> and V<sub>4</sub>, the "lifting" diode V<sub>5</sub> and the current-limiting resistor R<sub>3</sub> (see the figure on the right). It is driven by applying the same ''current steering'' idea as above.

When V<sub>2</sub> is "off", V<sub>4</sub> is "off" as well and V<sub>3</sub> operates in active region as a [[Common collector|voltage follower]] producing high output voltage (logical "1").

When V<sub>2</sub> is "on", it activates V<sub>4</sub>, driving low voltage (logical "0") to the output. Again there is a current-steering effect: the series combination of V<sub>2</sub>'s C-E junction and V<sub>4</sub>'s B-E junction is in parallel with the series of V<sub>3</sub> B-E, V<sub>5</sub>'s anode-cathode junction, and V<sub>4</sub> C-E. The second series combination has the higher threshold voltage, so no current flows through it, i.e. V<sub>3</sub> base current is deprived. Transistor V<sub>3</sub> turns "off" and it does not impact on the output.

In the middle of the transition, the resistor R<sub>3</sub> limits the current flowing directly through the series connected transistor V<sub>3</sub>, diode V<sub>5</sub> and transistor V<sub>4</sub> that are all conducting. It also limits the output current in the case of output logical "1" and short connection to the ground. The strength of the gate may be increased without proportionally affecting the power consumption by removing the pull-up and pull-down resistors from the output stage.<ref>[http://www.siliconfareast.com/ttl.htm ''Transistor–Transistor Logic (TTL).''] siliconfareast.com. 2005. Retrieved 17 September 2008. p. 1.</ref><ref>Tala, D. K. [http://www.asic-world.com/digital/gates5.html ''Digital Logic Gates Part-V.''] asic-world.com. 2006.</ref>

The main advantage of TTL with a "totem-pole" output stage is the low output resistance at output logical "1". It is determined by the upper output transistor V<sub>3</sub> operating in active region as an [[emitter follower]]. The resistor R<sub>3</sub> does not increase the output resistance since it is connected in the V<sub>3</sub> collector and its influence is compensated by the negative feedback. A disadvantage of the "totem-pole" output stage is the decreased voltage level (no more than 3.5 V) of the output logical "1" (even if the output is unloaded). The reasons for this reduction are the voltage drops across the V<sub>3</sub> base–emitter and V<sub>5</sub> anode–cathode junctions.