Editing SuperH (section)

===Licensing===
In early 2001, Hitachi and STM formed the [[patent holding company|IP company]] SuperH, Inc., which was going to license the SH-4 core to other companies and was developing the SH-5 architecture, the first move of SuperH into the 64-bit area. The earlier SH-1 through 3 remained the property of Hitachi.<ref name=sh5>{{cite web |title=STMicro, Hitachi plan new company to develop RISC cores|url=http://www.eetimes.com/document.asp?doc_id=1180485 |date=3 April 2001 |website=EE Times|quote=Hitachi created the SH family of processors and developed its first four major iterations, but has worked with ST since 1997, when the companies agreed to share a common high-end microprocessor road map. They jointly developed the 32-bit SH4 RISC processor core, and began development of the SH5 architecture, which will now be completed by SuperH. SuperH's initial product will be the SH4 core. Earlier SH versions will not be part of the spin-off agreement.}}</ref><ref>{{cite web|title=SuperH, Inc. formed by Hitachi and STMicroelectronics to Boost the Proliferation of SuperH Cores in Embedded Microprocessor Applications|url=http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682|archive-url=https://archive.today/20160219085937/http://investors.st.com/phoenix.zhtml?c=111941&p=irol-newsArticle_print&ID=1454682|url-status=dead|archive-date=February 19, 2016}}</ref>

In 2003, Hitachi and [[Mitsubishi Electric]] formed a joint-venture called [[Renesas Electronics|Renesas Technology]], with Hitachi controlling 55% of it. In 2004, Renesas Technology bought STMicroelectronics's share of ownership in the SuperH Inc. and with it the licence to the SH cores.<ref>{{cite web|url=https://www.eetimes.com/renesas-to-take-over-superh-core-business/|date=28 September 2004|website=EE Times|title=Renesas to take over SuperH core business |first=Peter |last=Clarke}}</ref> Renesas Technology later became Renesas Electronics, following their merger with [[NEC Electronics]].

The SH-5 design supported two modes of operation: SHcompact mode, which is equivalent to the user-mode instructions of the SH-4 instruction set; and SHmedia mode, which is very different in that it uses 32-bit instructions with sixty-four 64-bit integer registers and [[Single instruction, multiple data|SIMD]] instructions. In SHmedia mode the destination of a [[branch (computer science)|branch]] (jump) is loaded into a branch register separately from the actual branch instruction. This allows the processor to prefetch instructions for a branch without having to snoop the instruction stream. The combination of a compact 16-bit instruction encoding with a more powerful 32-bit instruction encoding is not unique to SH-5; [[ARM architecture|ARM]] processors have a 16-bit [[ARM architecture#Thumb|Thumb]] mode (ARM licensed several patents from SuperH for Thumb<ref name="lwn"/>) and [[MIPS architecture|MIPS]] processors have a MIPS-16 mode. However, SH-5 differs because its backward compatibility mode is the 16-bit encoding rather than the 32-bit encoding.

The last evolutionary step happened around 2003 where the cores from SH-2 up to SH-4 were getting unified into a superscalar SH-X core which formed a kind of instruction set superset of the previous architectures, and added support for [[symmetric multiprocessing]].