Editing SPARC (section)

===Instruction formats===
All SPARC instructions occupy a full 32-bit word and start on a word boundary. Four formats are used, distinguished by the first two bits. All arithmetic and logical instructions have 2 source operands and 1 destination operand.<ref name=ncsu>{{cite web |url=https://arcb.csc.ncsu.edu/~mueller/codeopt/codeopt00/notes/sparc.html |title= SPARC Fundamental Instructions}}</ref> RD is the "destination register", where the output of the operation is deposited. The majority of SPARC instructions have at least this register, so it is placed near the "front" of the instruction format. RS1 and RS2 are the "source registers", which may or may not be present, or replaced by a constant.

{| class="wikitable" style="text-align:center;"
|+ SPARC instruction formats
|-
! rowspan=2  | Type
! colspan=32 | Bit
|-
! 31 !! 30 !! 29 !! 28 !! 27 !! 26 !! 25 !! 24 !! 23 !! 22 !! 21 !! 20 !! 19 !! 18 !! 17 !! 16 !! 15 !! 14 !! 13 !! 12 !! 11 !! 10 !! 9 !! 8 !! 7 !! 6 !! 5 !! 4 !! 3  !! 2 !! 1 !! 0
|-
| SETHI format ||colspan="2"|00||colspan="5"| RD || colspan="3"|100 ||colspan="22"|Immediate constant 22 bits
|-
| I Branch format ||colspan="2"|00||A||colspan="4"|icc||colspan="3"|010||colspan="22"|Displacement constant 22 bits
|-
| F Branch format ||colspan="2"|00||A||colspan="4"|fcc||colspan="3"|110 ||colspan="22"|Displacement constant 22 bits
|-
| C Branch format ||colspan="2"|00||A||colspan="4"|ccc||colspan="3"|111 ||colspan="22"|Displacement constant 22 bits
|-
| CALL disp ||colspan="2"|01||colspan="30"|PC-relative displacement
|-
| Arithmetic register ||colspan="2"|10||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 0 || colspan="8"|0 ||colspan="5"| RS2
|-
| Arithmetic immediate ||colspan="2"|10||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 1 || colspan="13"| Immediate constant 13 bits
|-
| FPU operation ||colspan="2"|10||colspan="5"| FD || colspan="6"|110100/110101 ||colspan="5"| FS1 || colspan="9"| opf ||colspan="5"| FS2
|-
| CP operation ||colspan="2"|10||colspan="5"| RD || colspan="6"|110110/110111 ||colspan="5"| RS1 || colspan="9"| opc ||colspan="5"| RS2
|-
| JMPL register ||colspan="2"|10||colspan="5"| RD || colspan="6"|111000 ||colspan="5"| RS1 || 0 || colspan="8"|0 ||colspan="5"| RS2
|-
| JMPL immediate ||colspan="2"|10||colspan="5"| RD || colspan="6"|111000 ||colspan="5"| RS1 || 1 || colspan="13"| Immediate constant 13 bits
|-
| LD/ST register ||colspan="2"|11||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 0 || colspan="8"|0 ||colspan="5"| RS2
|-
| LD/ST immediate ||colspan="2"|11||colspan="5"| RD || colspan="6"|opcode ||colspan="5"| RS1 || 1 || colspan="13"| Immediate constant 13 bits
|}