Editing Protected mode (section)

== Entering and exiting protected mode ==

Until the release of the 386, protected mode did not offer a direct method to switch back into real mode once protected mode was entered. [[IBM]] devised a workaround (implemented in the [[IBM Personal Computer AT|IBM AT]]) which involved resetting the CPU via the keyboard controller and saving the system registers, [[call stack|stack pointer]] and often the interrupt mask in the real-time clock chip's RAM.  This allowed the BIOS to restore the CPU to a similar state and begin executing code before the reset.{{Clarify|date=August 2011}} Later, a [[triple fault]] was used to reset the 286 CPU, which was a lot faster and cleaner than the keyboard controller method.

To enter protected mode, the [[Global Descriptor Table]] (GDT) must first be created with a minimum of three entries: a null descriptor, a code segment descriptor and data segment descriptor. Then, the PE bit must be set in the CR0 register and a far jump must be made to clear the [[prefetch input queue]].<ref>{{Cite web|title=Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide|at=9.9.1 Switching to Protected Mode, page 9-13|language=en|publisher=[[Intel]]|url=https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide}}</ref><ref>{{Cite web|title=Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide|at=Section 9.10.2 STARTUP.ASM Listing, page 9-19|language=en|publisher=[[Intel]]|url=https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide}}</ref> Also, on an IBM-compatible machine, in order to enable the CPU to access all 16 MB of the address space (instead of only the 8 even megabytes), the [[A20 line]] (21st address line) must be enabled. (A20 is disabled at power-up, causing each odd megabyte of the address space to be aliased to the previous even megabyte, in order to guarantee compatibility with older software written for the Intel 8088-based [[IBM Personal Computer|IBM PC]] and [[IBM Personal Computer XT|PC/XT]] models).<ref>{{Cite web|title=Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide|at=Section 21.33.1 Segment Wraparound, page 21-34|language=en|publisher=[[Intel]]|url=https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide}}</ref> Enabling A20 is not strictly required to run in protected mode; the CPU will operate normally in protected mode with A20 disabled, only without the ability to access half of the memory addresses.

<syntaxhighlight lang="nasm">
; MASM program
; enter protected mode (set PE bit)
mov EBX, CR0   ; save control register 0 (CR0) to EBX
or EBX, PE_BIT ; set PE bit by ORing, save to EBX
mov CR0, EBX   ; save EBX back to CR0

; clear prefetch queue; (using far jump instruction jmp)
jmp CLEAR_LABEL
CLEAR_LABEL:
</syntaxhighlight>

With the release of the 386, protected mode could be exited by loading the segment registers with real mode values, disabling the A20 line and clearing the PE bit in the CR0 register, without the need to perform the initial setup steps required with the 286.
<ref>{{Cite web|title=Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes 3A, 3B, 3C, and 3D: System Programming Guide|at=Section 9.9.2 Switching Back to Real-Address Mode, page 9-14|language=en|publisher=[[Intel]]|url=https://software.intel.com/en-us/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide}}</ref>