Editing Meiko Scientific (section)

==CS-2==
The CS-2<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/brochures/CS-2_Product_Description.pdf CS-2 Product Description] Meiko; 1993</ref><ref>[https://web.archive.org/web/20010709110330/http://www.top500.org/ORSC/1998/cs-2.html Top500 description of the CS-2] Top500.org; 1998</ref><ref>''CS-2: Predatory Computing Performance'', Meiko Limited; 1992</ref> was launched in 1993 and was Meiko's second-generation system architecture, superseding the earlier Computing Surface.

The CS-2 was an all-new modular architecture based around [[SPARC|SuperSPARC]] or [[hyperSPARC]] processors<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/cs-2/CS-2_Hardware_Reference_Manuals_1995.pdf CS-2_Hardware_Reference_Manuals] Meiko; 1995</ref> and, optionally, [[Fujitsu]] μVP [[vector processor]]s.<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/cs-2/MK403.pdf MK403 Manual] Meiko; 1993</ref> These implemented an instruction set similar to the [[Fujitsu VP2000]] vector supercomputer and had a nominal performance of 200 [[megaflops]] on [[double precision]] arithmetic and double that on [[single precision]]. The SuperSPARC processors ran at 40&nbsp;MHz initially, later increased to 50&nbsp;MHz. Subsequently, hyperSPARC processors were introduced at 66, 90 or 100&nbsp;MHz. The CS-2 was intended to scale up to 1024 processors. The largest CS-2 system built was a 224-processor system<ref>{{cite web
|url=http://www.top500.org/system/1607
|title=CS-2/224 at Lawrence Livermore National Laboratory
}}</ref> installed at [[Lawrence Livermore National Laboratory]].

The CS-2 ran a customized version of Sun's operating system [[Solaris (operating system)|Solaris]], initially Solaris 2.1, later 2.3 and 2.5.1.

===Elan-Elite Interconnect===
The processors in a CS-2 were connected by a Meiko-designed multi-stage packet-switched ''[[fat tree]]'' network implemented in custom silicon.<ref>[http://portal.acm.org/citation.cfm?id=196892 Meiko CS-2 Interconnect Elan-Elite design] Jon Beecroft, Fred Homewood, Moray McLaren; Journal Parallel Computing; Volume 20 Issue 10-11, November 1994</ref><ref>[http://dl.acm.org/citation.cfm?id=196892 Meiko CS-2 Interconnect Elan-Elite design] Fred Homewood, Moray McLaren; Hot Interconnects Conference, Stanford; August 1993</ref><ref>[http://www.netlib.org/utk/people/JackDongarra/journals/088_1997_message-passing-performance-of-various-computers.pdf Message Passing Performance] Jack Dongarra and Tom Dunigan; Concurrancy: Practice and Experience; October 1997</ref>

This project, codenamed Elan-Elite, was started in 1990, as a speculative project to compete with the T9000 [[Transputer]] from [[Inmos]], which Meiko intended to use as an interconnect technology. The [[Transputer|T9000]] began to suffer massive delays, such that the internal project became the only viable interconnect choice for the CS-2.

This interconnect comprised two devices, code-named ''Elan'' ([[Network interface controller|adapter]]) and ''Elite'' ([[Network switch|switch]]). Each processing element included an Elan chip, a communications co-processor based on the [[SPARC]] architecture, accessed via a [[MBus (SPARC)|Sun MBus]] [[cache coherence|cache coherent]] interface and providing two 50&nbsp;MB/s bi-directional links. The Elite chip was an 8-way link [[crossbar switch]], used to form the [[packet-switched network]]. The switch had limited adaption based on load and priority.<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/cs-2/S1002-10M105.05_Communications_Network_Overview_1993.pdf Communications Network Overview] Meiko Limited; 1993</ref>

Both ASICs were fabbed in complementary metal–oxide–semiconductor ([[CMOS]]) gate arrays by [[GEC Plessey Telecommunications|GEC Plessey]] in their [[Roborough, South Hams|Roborough]], [[Plymouth]] semi-conductor fab in 1993.

After the Meiko technology was acquired by [[Quadrics (company)|Quadrics]], the Elan/Elite interconnect technology was developed into [[QsNet]].