Editing MOS Technology 6502 (section)

===Moving to NMOS===
Two significant advances arrived in the market just as the 6502 was being designed that provided significant cost reductions. The first was the move to [[depletion-load NMOS]]. The 6800 used an early [[NMOS logic|NMOS]] process, enhancement mode, that required three supply voltages. One of the 6800's headlining features was an onboard [[voltage doubler]] that allowed a single +5&nbsp;V supply be used for +5, −5 and +12&nbsp;V internally, as opposed to other chips of the era like the [[Intel 8080]] that required three separate supply pins.<ref>{{cite web |url=http://www.cpu-world.com/info/Pinouts/8080.html |website=CPU World |title=8080A microprocessor – DIP 40 package |access-date=2020-02-24 |archive-date=2020-09-15 |archive-url=https://web.archive.org/web/20200915164812/http://www.cpu-world.com/info/Pinouts/8080.html |url-status=live}}</ref> While this feature reduced the complexity of the power supply and pin layout, it still required separate power line to the various gates on the chip, driving up complexity and size. By moving to the new depletion-load design, a single +5&nbsp;V supply was all that was needed, eliminating all of this complexity.{{sfn|Cushman|1975|p=38}}

A further advantage was that depletion-load designs used less power while switching, thus running cooler and allowing higher operating speeds. Another practical offshoot is that the clock signal for earlier CPUs had to be strong enough to survive all the dissipation as it traveled through the circuits, which almost always required a separate external chip that could supply a powerful signal. With the reduced power requirements of depletion-load design, the clock could be moved onto the chip, simplifying the overall computer design. These changes greatly reduced complexity and the cost of implementing a complete system.{{sfn|Cushman|1975|p=38}}

A wider change taking place in the industry was the introduction of [[projection mask]]ing. Previously, chips were patterned onto the surface of the wafer by placing a [[photomask|mask]] on the surface of the wafer and then shining a bright light on it. The masks often picked up tiny bits of dirt or [[photoresist]] as they were lifted off the chip, causing flaws in those locations on any subsequent masking. With complex designs like CPUs, 5 or 6 such masking steps would be used, and the chance that at least one of these steps would introduce a flaw was very high. In most cases, 90% of such designs were flawed, resulting in a 10% yield. The price of the working examples had to cover the production cost of the 90% that were thrown away.<ref name=milestone>{{cite web |url=https://spectrum.ieee.org/moores-law-milestones |title=Moore's Law Milestones |website=IEEE |date=30 April 2015 |access-date=2020-02-24 |archive-date=2020-02-24 |archive-url=https://web.archive.org/web/20200224213400/https://spectrum.ieee.org/tech-history/silicon-revolution/moores-law-milestones |url-status=live}}</ref>

In 1973, [[Perkin-Elmer]] introduced the [[Micralign]] system, which projected an image of the mask on the wafer instead of requiring direct contact. Masks no longer picked up dirt from the wafers and lasted on the order of 100,000 uses rather than 10. This eliminated step-to-step failures and the high flaw rates formerly seen on complex designs. Yields on CPUs immediately jumped from 10% to 60 or 70%. This meant the price of the CPU declined roughly the same amount and the microprocessor suddenly became a commodity device.<ref name=milestone/>

MOS Technology's existing fabrication lines were based on the older [[PMOS logic|PMOS]] technology, they had not yet begun to work with [[NMOS logic|NMOS]] when the team arrived. Paivinen promised to have an NMOS line up and running in time to begin the production of the new CPU. He delivered on the promise, the new line was ready by June 1975.<ref>Bagnall (2010), p. 19: "Paivinen promised Peddle he would have the n-channel process ready. He was true to his word."</ref>