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===Opteron (32 nm SOI) β ''Piledriver'' microarchitecture=== {{Main|Piledriver (microarchitecture)}} ====Quad-core β ''Delhi'' (3320 EE, 3350 HE)==== Released December 4, 2012. * CPU steppings: C0 * Single die consisting of two [[Piledriver (microarchitecture)|Piledriver]] modules * L2 cache: 2 Γ 2 MB * L3 cache: 8 MB, shared * Clockrate: 1.9 GHz (3320 EE) β 2.8 GHz (3350 HE) * 1 Γ HyperTransport 3 (5.2 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, up to 2.5 GHz (3320 EE), up to 3.8 GHz (3350 HE) * Supports uniprocessor configurations only * [[Socket AM3+]] ====Eight-core β ''Delhi'' (3380)==== Released December 4, 2012. * CPU steppings: C0 * Single die consisting of four [[Piledriver (microarchitecture)|Piledriver]] modules * L2 cache: 4 Γ 2 MB * L3 cache: 8 MB, shared * Clock rate: 2.6 GHz * 1 Γ HyperTransport 3 (5.2 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, pp to 3.6 GHz * Supports uniprocessor configurations only * [[Socket AM3+]] ==== 4-core β ''Seoul'' (4310 EE)==== Released December 4, 2012 * CPU steppings: C0 * Single die consisting of two [[Piledriver (microarchitecture)|Piledriver]] modules * L2 cache: 2 Γ 2 MB * L3 cache: 8 MB, shared * Clock rate: 2.2 GHz * 2 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, up to 3.0 GHz * Supports up to dual-processor configurations * [[Socket C32]] ====6-core β ''Seoul'' (4332 HE β 4340)==== Released December 4, 2012 * CPU steppings: C0 * Single die consisting of three [[Piledriver (microarchitecture)|Piledriver]] modules * L2 cache: 3 Γ 2 MB * L3 cache: 8 MB, shared * Clockrate: 3.0 GHz (4332 HE) β 3.5 GHz (4340) * 2 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, from 3.5 GHz (4334) to 3.8 GHz (4340) * Supports up to dual-processor configurations * [[Socket C32]] ==== 8-core β ''Seoul'' (4376 HE and above)==== Released December 4, 2012 * CPU steppings: C0 * Single die consisting of four [[Piledriver (microarchitecture)|Piledriver]] modules * L2 cache: 4 Γ 2 MB * L3 cache: 8 MB, shared * Clock rate: 2.6 GHz (4376 HE) β 3.1 GHz (4386) * 2 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, from 3.6 GHz (4376 HE) to 3.8 GHz (4386) * Supports up to dual-processor configurations * [[Socket C32]] ==== Quad-core β ''Abu Dhabi'' MCM (6308)==== Released November 5, 2012. * CPU steppings: C0 * Multi-chip module consisting of two dies, each with one [[Piledriver (microarchitecture)|Piledriver]] module * L2 cache: 2 MB per die (4 MB total) * L3 cache: 2 Γ 8 MB, shared within each die * Clock rate: 3.5 GHz * 4 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Does not support Turbo CORE * Supports up to quad-processor configurations * [[Socket G34]] ==== Eight-core β ''Abu Dhabi'' MCM (6320, 6328)==== Released November 5, 2012. * CPU steppings: C0 * Multi-chip module consisting of two dies, each with two [[Piledriver (microarchitecture)|Piledriver]] module * L2 cache: 2 Γ 2 MB per die (8 MB total) * L2 cache: 2 Γ 8 MB, shared within each die * Clock rate: 2.8 GHz (6320) β 3.2 GHz (6328) * 4 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, from 3.3 GHz (6320) to 3.8 GHz (6328) * Supports up to quad-processor configurations * [[Socket G34]] ====12-core β ''Abu Dhabi'' MCM (6344, 6348)==== Released November 5, 2012. * CPU steppings: C0 * Multi-chip module consisting of two dies, each with three [[Piledriver (microarchitecture)|Piledriver]] module * L2 cache: 3 Γ 2 MB per die (12 MB total) * L3 cache: 2 Γ 8 MB, shared within each die * Clock rate: 2.6 GHz (6344) β 2.8 GHz (6348) * 4 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, from 3.2 GHz (6344) to 3.4 GHz (6348) * Supports up to quad-processor configurations * [[Socket G34]] ==== 16-core β ''Abu Dhabi'' MCM (6366 HE and above)==== Released November 5, 2012. * CPU steppings: C0 * Multi-chip module consisting of two dies, each with four [[Piledriver (microarchitecture)|Piledriver]] module * L2 cache: 4 Γ 2 MB per die (16 MB total) * L3 cache: 2 Γ 8 MB, shared within each die * Clock rate: 1.8 GHz (6366 HE) β 2.8 GHz (6386 SE) * 4 Γ HyperTransport 3.1 at 3.2 GHz (6.40 GT/s per link) * HT Assist * Support for DDR3 1866 MHz memory * Turbo CORE support, from 3.1 GHz (6366 HE) to 3.5 GHz (6386 SE) * Supports up to quad-processor configurations * [[Socket G34]]
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