Editing PCI Express (section)

=== Efficiency of the link ===
As for any network-like communication links, some of the raw bandwidth is consumed by protocol overhead:<ref name="Xilinx">{{cite web|title=Understanding Performance of PCI Express Systems|url=https://www.xilinx.com/support/documentation/white_papers/wp350.pdf|last=Lawley|first=Jason|publisher=Xilinx|version=1.2|date=2014-10-28}}</ref>

A PCIe 1.x lane for example offers a data rate on top of the physical layer of 250&nbsp;MB/s (simplex). This is not the payload bandwidth but the physical layer bandwidth – a PCIe lane has to carry additional information for full functionality.{{r|Xilinx}}

{| class="wikitable"
|+Gen 2 Transaction Layer Packet{{r|Xilinx|p=3}}
!scope="row" scope="col" style="width: 80px;" |Layer
!scope="col" style="width: 20px;" |PHY
!scope="col" style="width: 120px;" |Data Link Layer
!scope="col" style="width: 400px;" colspan="3" |Transaction
!scope="col" style="width: 120px;" |Data Link Layer
!scope="col" style="width: 20px;" |PHY
|-
!scope="row" |Data
|Start
|Sequence
|scope="col" style="width: 75px;" |Header
|scope="col" style="text-align:center; width: 250px;" |Payload
|scope="col" style="width: 75px;" |ECRC
|LCRC
|End
|-
!scope="row" |Size (Bytes)
|1
|2
|12 or 16
|scope="col" style="text-align:center;" |0 to 4096
|4 (optional)
|4
|1
|}
The Gen2 overhead is then 20, 24, or 28 bytes per transaction.{{Clarify |reason=Don't we also have a 8/10b encoding overhead that's not factored in to any of this?|date=September 2021}}{{Citation needed|reason=I fixed the bad math here, but it needs a source, not me and a calculator|date=September 2021}}

{| class="wikitable"
|+Gen 3 Transaction Layer Packet{{r|Xilinx|p=3}}
!scope="row" scope="col" style="width: 80px;" |Layer
!scope="col" style="width: 40px;" |PHY
!scope="col" style="width: 120px;" |Data Link Layer
!scope="col" colspan="3" style="width: 400px;" |Transaction Layer
!scope="col" style="width: 120px;" |Data Link Layer
|-
!scope="row" |Data
|Start
|Sequence
|scope="col" style="width: 75px;" |Header
|scope="col" style="width: 250px;text-align:center;" |Payload
|scope="col" style="width: 75px;" |ECRC
|LCRC
|-
!scope="row" |Size (Bytes)
|4
|2
|12 or 16
|scope="col" style="text-align:center; |0 to 4096
|4 (optional)
|4
|}
The Gen3 overhead is then 22, 26 or 30 bytes per transaction.<!-- Seriously how did somebody get odd numbers out of this? -->{{Clarify |reason=Don't we also have a 128/130b encoding overhead that's not factored in to any of this?|date=September 2021}}{{Citation needed|reason=I fixed the bad math here, but it needs a source, not me and a calculator|date=September 2021}}

The <math>\text{Packet Efficiency} = \frac{\text{Payload}}{\text{Payload} + \text{Overhead}}</math> for a 128 byte payload is 86%, and 98% for a 1024 byte payload. For small accesses like register settings (4 bytes), the efficiency drops as low as 16%.{{Citation needed|reason=Formula is in text, but it didn't state this anywhere or anything about register settings being 4 bytes or the like... and most of the PCIe config registers aren't on the devices and don't need a bus access, they're just sitting around in a DMA region mapped to the CPU's control registers|date=September 2021}}

The maximum payload size (MPS) is set on all devices based on smallest maximum on any device in the chain. If one device has an MPS of 128 bytes, ''all'' devices of the tree must set their MPS to 128 bytes. In this case the bus will have a peak efficiency of 86% for writes.{{r|Xilinx|p=3}}