Editing StrongARM (section)

==SA-1100==
The SA-1100 was a derivative of the SA-110 developed by DEC. Announced in 1997, the SA-1100 was targeted for portable applications such as PDAs and differs from the SA-110 by providing a number of features that are desirable for such applications. To accommodate these features, the data cache was reduced in size to 8&nbsp;KB.

The extra features are integrated memory, [[PCMCIA]], and color LCD controllers connected to an on-die system bus, and five serial I/O channels that are connected to a peripheral bus attached to the system bus. The memory controller supported FPM and EDO DRAM, SRAM, flash, and ROM. The PCMCIA controller supports two slots. The memory address and data bus is shared with the PCMCIA interface. Glue logic is required. The serial I/O channels implement a slave USB interface, a [[Synchronous Data Link Control|SDLC]], two [[UART]]s, an [[IrDA]] interface, a MCP, and a [[Synchronous Serial Port|synchronous serial port]].

The SA-1100 had a companion chip, the SA-1101. It was introduced by Intel on 7 October 1998.<ref>Intel Corporation (7 October 1998). "Intel Introduces StrongARM Products for PC Companions". Press release.</ref> The SA-1101 provided additional peripherals to complement those integrated on the SA-1100 such as a video output port, two [[PS/2 connector|PS/2]] ports, a USB controller and a PCMCIA controller that replaces that on the SA-1100. Design of the device started by DEC, but was only partially complete when acquired by Intel, who had to finish the design. It was fabricated at DEC's former [[Hudson, Massachusetts]] fabrication plant, which was also sold to Intel.<ref>{{cite web|url=http://www.mdronline.com/publications/epw/issues/epw_17.html|title=The Linley Group - The industry's leading experts in communications semiconductor markets|work=mdronline.com}}</ref>

The SA-1100 contained 2.5 million transistors and measured 8.24&nbsp;mm by 9.12&nbsp;mm (75.15&nbsp;mm<sup>2</sup>). It was fabricated in a 0.35&nbsp;μm CMOS process with three levels of [[aluminium interconnect]] and was packaged in a 208-pin TQFP.<ref name="ISSCC-1998">Stephany, R. et al. (1998). "A 200MHz 32b 0.5W CMOS RISC Microprocessor". ''ISSCC Digest of Technical Papers'', pp. 238&ndash;239, 443.</ref>

One of the early recipients of this processor was-ill-fated [[Psion netBook]] and its more consumer oriented sibling [[Psion Series 7]].