Editing Semiconductor device fabrication (section)

===21st century===
[[File:Intel Fab 12, Fab 22, Fab 32.jpg|thumb|Intel facilities in Chandler Arizona]]
The [[semiconductor industry]] is a global business today. The leading semiconductor manufacturers typically have facilities all over the world. [[Samsung Electronics]], the world's largest manufacturer of semiconductors, has facilities in South Korea and the US. [[Intel]], the second-largest manufacturer, has facilities in Europe and Asia as well as the US. [[TSMC]], the world's largest [[Foundry model|pure play foundry]], has facilities in Taiwan, China, Singapore, and the US. [[Qualcomm]] and [[Broadcom]] are among the biggest [[fabless]] semiconductor companies, outsourcing their production to companies like TSMC.<ref>{{Cite news|url=http://anysilicon.com/top-10-worldwide-semiconductor-sales-leaders-q1-2017/|title=Top 10 Worldwide Semiconductor Sales Leaders - Q1 2017 - AnySilicon|date=2017-05-09|work=AnySilicon|access-date=2017-11-19|language=en-US|archive-date=2017-11-06|archive-url=https://web.archive.org/web/20171106231204/http://anysilicon.com/top-10-worldwide-semiconductor-sales-leaders-q1-2017/|url-status=live}}</ref> They also have facilities spread in different countries. As the average utilization of semiconductor devices increased, durability became an issue and manufacturers started to design their devices to ensure they last for enough time, and this depends on the market the device is designed for. This especially became a problem at the 10&nbsp;nm node.<ref>{{Cite web|url=https://semiengineering.com/transistor-aging-intensifies-10nm/|title=Transistor Aging Intensifies At 10/7nm And Below|first=Ann|last=Mutschler|date=July 13, 2017|website=Semiconductor Engineering}}</ref><ref>{{Cite web|url=https://semiengineering.com/chip-aging-accelerates/|title=Chip Aging Accelerates|first=Ed|last=Sperling|date=February 14, 2018|website=Semiconductor Engineering}}</ref>

[[Silicon on insulator]] (SOI) technology has been used in [[AMD]]'s 130&nbsp;nm, 90&nbsp;nm, 65&nbsp;nm, 45&nbsp;nm and 32&nbsp;nm single, dual, quad, six and eight core processors made since 2001.<ref>{{cite web |last=de Vries |first=Hans |date= |title=Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed. |url=http://chip-architect.com/news/2000_11_07_process_130_nm.html |access-date=22 April 2018 |website=chip-architect.com}}</ref> During the transition from 200&nbsp;mm to 300&nbsp;mm wafers in 2001, many bridge tools were used which could process both 200&nbsp;mm and 300&nbsp;mm wafers.<ref>{{cite web | url=https://www.edn.com/bridge-tools-appear-to-be-taking-over-300-mm-movement/ | title='Bridge tools' appear to be taking over 300-mm movement | date=26 April 2001 }}</ref> At the time, 18 companies could manufacture chips in the leading edge 130nm process.<ref>{{cite web | url=https://semiengineering.com/foundry-wars-begin/ | title=Foundry Wars Begin | date=19 April 2021 }}</ref>

In 2006, 450&nbsp;mm wafers were expected to be adopted in 2012, and 675&nbsp;mm wafers were expected to be used by 2021.<ref>{{cite web | url=https://www.eetimes.com/get-ready-for-675-mm-fabs-in-2021/ | title=Get ready for 675-mm fabs in 2021 | date=14 November 2006 }}</ref>

[[File:Semiconductor photomask.jpg|thumb|Semiconductor photomask or reticle]]
Since 2009, "node" has become a commercial name for marketing purposes that indicates new generations of process technologies, without any relation to gate length, metal pitch or gate pitch.<ref>{{cite web|url=https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|title=A Brief History of Process Node Evolution|last=Shukla|first=Priyank|website=design-reuse.com|access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064439/https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html|url-status=live}}</ref><ref>{{cite news|url=https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|title=14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists…|last=Hruska|first=Joel|website=[[ExtremeTech]]|date=23 June 2014 |access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064438/https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists|url-status=live}}</ref><ref>{{cite web|url=https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|title=Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022|website=wccftech.com|date=2016-09-10|access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064438/https://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/|url-status=live}}</ref> For example, [[GlobalFoundries]]' [[7&nbsp;nm]] process was similar to Intel's [[10 nm process]], thus the conventional notion of a process node has become blurred.<ref>{{cite web|url=https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|title=Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms|website=eejournal.com|date=2018-03-12|access-date=2019-07-09|archive-date=2019-07-09|archive-url=https://web.archive.org/web/20190709064439/https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/|url-status=live}}</ref> Additionally, TSMC and Samsung's 10&nbsp;nm processes are only slightly denser than Intel's 14&nbsp;nm in transistor density. They are actually much closer to Intel's 14&nbsp;nm process than they are to Intel's 10&nbsp;nm process (e.g. Samsung's 10&nbsp;nm processes' fin pitch is the exact same as that of Intel's 14&nbsp;nm process: 42&nbsp;nm).<ref>{{Cite web|url=https://en.wikichip.org/wiki/10_nm_lithography_process#Industry|title=10 nm lithography process - WikiChip|website=en.wikichip.org|access-date=2019-08-17|archive-date=2019-07-01|archive-url=https://web.archive.org/web/20190701083338/https://en.wikichip.org/wiki/10_nm_lithography_process#Industry|url-status=live}}</ref><ref>{{Cite web|url=https://en.wikichip.org/wiki/14_nm_lithography_process#Industry|title=14 nm lithography process - WikiChip|website=en.wikichip.org|access-date=2019-08-17|archive-date=2019-07-01|archive-url=https://web.archive.org/web/20190701083339/https://en.wikichip.org/wiki/14_nm_lithography_process#Industry|url-status=live}}</ref> Intel has changed the name of its 10&nbsp;nm process to position it as a 7&nbsp;nm process.<ref>{{cite web | url=https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros | title=Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?! | last=Cutress | first=Ian | website=[[AnandTech]]}}</ref> As transistors become smaller, new effects start to influence design decisions such as self-heating of the transistors, and other effects such as electromigration have become more evident since the 16nm node.<ref>{{Cite web|url=https://semiengineering.com/chip-aging-becomes-design-problem/|title=Chip Aging Becomes Design Problem|first=Brian|last=Bailey|date=August 9, 2018|website=Semiconductor Engineering}}</ref><ref>{{Cite web|url=https://semiengineering.com/will-self-heating-stop-finfets/|title=Will Self-Heating Stop FinFETs|first=Katherine|last=Derbyshire|date=April 20, 2017|website=Semiconductor Engineering}}</ref>

In 2011, [[Intel]] demonstrated [[Fin field-effect transistor]]s (FinFETs), where the gate surrounds the channel on three sides, allowing for increased energy efficiency and lower gate delay—and thus greater performance—over planar transistors at the 22nm node, because planar transistors which only have one surface acting as a channel, started to suffer from short channel effects.<ref>{{cite web | url=https://semiengineering.com/knowledge_centers/integrated-circuit/transistors/3d/finfet-3/ | title=FinFET }}</ref><ref>{{cite web | url=https://spectrum.ieee.org/foundries-rush-3d-transistors | title=Foundries Rush 3-D Transistors - IEEE Spectrum }}</ref><ref>{{Cite web|url=http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf|title=Intel's Revolutionary 22 nm Transistor Technology|last1=Bohr|first1=Mark|last2=Mistry|first2=Kaizad|date=May 2011|website=intel.com|access-date=April 18, 2018}}</ref><ref>{{Cite news|url=https://www.techradar.com/news/computing-components/processors/intel-s-tri-gate-transistors-everything-you-need-to-know-952572|title=Intel's Tri-Gate transistors: everything you need to know|last=Grabham|first=Dan|date=May 6, 2011|work=TechRadar|access-date=April 19, 2018}}</ref><ref>
{{cite journal |doi=10.1109/MM.2017.4241347|title=CMOS Scaling Trends and Beyond|journal=IEEE Micro|volume=37|issue=6|pages=20–29|year=2017|last1=Bohr|first1=Mark T.|last2=Young|first2=Ian A.
|s2cid=6700881|quote=The next major transistor innovation was the introduction of FinFET (tri-gate) transistors on Intel's 22-nm technology in 2011.}}
</ref> A startup called SuVolta created a technology called Deeply Depleted Channel (DDC) to compete with FinFET transistors, which uses planar transistors at the 65&nbsp;nm node which are very lightly doped.<ref>{{cite web | url=https://spectrum.ieee.org/startup-seeks-new-life-for-planar-transistors | title=Start-up Seeks New Life for Planar Transistors - IEEE Spectrum }}</ref>

By 2018, a number of transistor architectures had been proposed for the eventual replacement of [[FinFET]], most of which were based on the concept of [[GAAFET]]:<ref>{{cite web | url=https://semiengineering.com/the-increasingly-uneven-race-to-3nm-2nm/ | title=The Increasingly Uneven Race to 3nm/2nm | date=24 May 2021 }}</ref> horizontal and vertical nanowires, horizontal nanosheet transistors<ref>{{cite web | url=https://semiengineering.com/whats-different-about-next-gen-transistors/ | title=What's Different About Next-Gen Transistors | date=20 October 2022 }}</ref><ref>{{cite web | url=https://spectrum.ieee.org/amp/intels-stacked-nanosheet-transistors-could-be-the-next-step-in-moores-law-2652903505 | title=Intel's Stacked Nanosheet Transistors Could be the Next Step in Moore's Law }}</ref> (Samsung MBCFET, Intel Nanoribbon), vertical FET (VFET) and other vertical transistors,<ref>{{cite web | url=https://spectrum.ieee.org/amp/nanowire-transistors-could-keep-moores-law-alive-2650269271 | title=Nanowire Transistors Could Keep Moore's Law Alive }}</ref><ref>{{cite web | url=https://physicsworld.com/a/nanowires-give-vertical-transistors-a-boost/ | title=Nanowires give vertical transistors a boost | date=2 August 2012 }}</ref> complementary FET (CFET), stacked FET, vertical TFETs, FinFETs with III-V semiconductor materials (III-V FinFET),<ref>{{cite web | url=https://arstechnica.com/gadgets/2016/07/itrs-roadmap-2021-moores-law/?amp=1 | title=Transistors will stop shrinking in 2021, but Moore's law will live on | date=25 July 2016 }}</ref><ref>{{Cite web|url=https://www.extremetech.com/science/162376-7nm-5nm-3nm-the-new-materials-and-transistors-that-will-take-us-to-the-limits-of-moores-law|title=7nm, 5nm, 3nm: The new materials and transistors that will take us to the limits of Moore's law &#124; Extremetech|date=26 July 2013 }}</ref> several kinds of horizontal gate-all-around transistors such as nano-ring, hexagonal wire, square wire, and round wire gate-all-around transistors<ref>{{cite web | url=https://semiengineering.com/whats-after-finfets/ | title=What's After FinFETs? | date=24 July 2017 }}</ref> and negative-capacitance FET (NC-FET) which uses drastically different materials.<ref>{{cite web | url=https://semiengineering.com/transistor-options-beyond-3nm/ | title=Transistor Options Beyond 3nm | date=15 February 2018 }}</ref> FD-SOI was seen as a potential low cost alternative to FinFETs.<ref>{{cite web | url=https://www.eetimes.com/samsung-gf-ramp-fd-soi/ | title=Samsung, GF Ramp FD-SOI | date=27 April 2018 }}</ref>

As of 2019, [[14 nanometer]] and [[10 nanometer]] chips are in mass production by Intel, [[United Microelectronics Corporation|UMC]], TSMC, Samsung, [[Micron Technology|Micron]], [[SK Hynix]], [[Toshiba Memory]] and GlobalFoundries, with [[7 nanometer]] process chips in mass production by TSMC and Samsung, although their 7 nanometer node definition is similar to Intel's 10 nanometer process. The [[5 nanometer]] process began being produced by Samsung in 2018.<ref>{{Cite web|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=[[AnandTech]]|access-date=2019-05-31|archive-date=2019-04-20|archive-url=https://web.archive.org/web/20190420144452/https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|url-status=live}}</ref> As of 2019, the node with the highest [[transistor density]] is TSMC's 5{{nbsp}}nanometer N5 node,<ref>{{cite web |last1=Cheng |first1=Godfrey |title=Moore's Law is not Dead |url=https://www.tsmc.com/english/news-events/blog-article-20190814 |website=TSMC Blog |publisher=[[TSMC]] |date=14 August 2019 |access-date=25 September 2023}}</ref> with a density of 171.3{{nbsp}}million transistors per square millimeter.<ref>{{Cite web|url=https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/|title=TSMC Starts 5-Nanometer Risk Production|last=Schor|first=David|date=2019-04-06|website=WikiChip Fuse|language=en-US|access-date=2019-04-07|archive-date=2020-05-05|archive-url=https://web.archive.org/web/20200505020415/https://fuse.wikichip.org/news/2207/tsmc-starts-5-nanometer-risk-production/|url-status=live}}</ref> In 2019, Samsung and TSMC announced plans to produce [[3 nanometer]] nodes. GlobalFoundries has decided to stop the development of new nodes beyond 12 nanometers in order to save resources, as it has determined that setting up a new fab to handle sub-12&nbsp;nm orders would be beyond the company's financial abilities.<ref>{{Cite web|url=https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development|title=GlobalFoundries Stops All 7nm Development: Opts To Focus on Specialized Processes|first1=Anton|last1=Shilov|first2=Ian|last2=Cutress|website=[[AnandTech]]|access-date=2019-10-12|archive-date=2019-10-12|archive-url=https://web.archive.org/web/20191012175428/https://www.anandtech.com/show/13277/globalfoundries-stops-all-7nm-development|url-status=live}}</ref>

From 2020 to 2022, there was a [[Global chip shortage (2020–2023)|global chip shortage]]. During this shortage caused by the COVID-19 pandemic, many semiconductor manufacturers banned employees from leaving company grounds.<ref>{{cite news | url=https://www.telegraph.co.uk/world-news/2021/06/25/taiwan-chipmakers-keep-workers-imprisoned-factories-keep-global/ | title=Taiwan chipmakers keep workers 'imprisoned' in factories to keep up with global pandemic demand | newspaper=The Telegraph | date=July 2021 | last1=Smith | first1=Nicola | last2=Liu | first2=John }}</ref> Many countries granted subsidies to semiconductor companies for building new fabrication plants or fabs. Many companies were affected by counterfeit chips.<ref>{{cite web | url=https://arstechnica.com/gadgets/2021/06/chip-shortages-lead-to-more-counterfeit-chips-and-devices/?amp=1 | title=Chip shortages lead to more counterfeit chips and devices | date=14 June 2021 }}</ref> Semiconductors have become vital to the world economy and the national security of some countries.<ref>{{cite interview|url=https://www.weforum.org/podcasts/radio-davos/episodes/silicon-chips-semiconductors-chris-miller/|title=What are semiconductors, and why are they vital to the global economy?|first=Chris|last=Miller|website=[[World Economic Forum]]}}</ref><ref>{{cite news|url=https://www.washingtonpost.com/technology/2021/06/14/global-subsidies-semiconductors-shortage/|title=Countries lavish subsidies and perks on semiconductor manufacturers as a global chip war heats up|first=Jeanne|last=Whalen|date=June 14, 2021|newspaper=[[The Washington Post]]}}</ref><ref>{{cite news|url=https://www.reuters.com/technology/us-launching-semiconductor-supply-chain-review-boost-national-security-2023-12-21/|title=China import concerns spur US to launch semiconductor supply chain review|first=David|last=Shepardson|date=December 21, 2023|website=Reuters}}</ref> The US has asked TSMC to not produce semiconductors for Huawei, a Chinese company.<ref>{{cite news | url=https://www.ft.com/content/6ab43e94-fca8-11e9-a354-36acbbb0d9b6 | title=US urges Taiwan to curb chip exports to China | newspaper=Financial Times | date=3 November 2019 | last1=Hille | first1=Kathrin }}</ref> CFET transistors were explored, which stacks NMOS and PMOS transistors on top of each other. Two approaches were evaluated for constructing these transistors: a monolithic approach which built both types of transistors in one process, and a sequential approach which built the two types of transistors separately and then stacked them.<ref name="auto10">{{cite web | url=https://semiwiki.com/events/300552-vlsi-technology-forum-short-course-logic-devices/ | title=VLSI Symposium - TSMC and Imec on Advanced Process and Devices Technology Toward 2nm | date=25 February 2024 }}</ref>