Editing SPARC (section)

===Registers===
The SPARC architecture has an overlapping register window scheme. At any instant, 32 general-purpose registers are visible. A Current Window Pointer (''CWP'') variable in the hardware points to the current set. The total size of the register file is not part of the architecture, allowing more registers to be added as the technology improves, up to a maximum of 32 windows in SPARC V7 and V8 as ''CWP'' is 5 bits and is part of the ''PSR'' register.

In SPARC V7 and V8 ''CWP'' will usually be decremented by the SAVE instruction (used by the SAVE instruction during the procedure call to open a new stack frame and switch the register window), or incremented by the RESTORE instruction (switching back to the call before returning from the procedure). Trap events ([[interrupt]]s, exceptions or TRAP instructions) and RETT instructions (returning from traps) also change the ''CWP''. For SPARC V9, CWP register is decremented during a RESTORE instruction, and incremented during a SAVE instruction. This is the opposite of PSR.CWP's behavior in SPARC V8. This change has no effect on nonprivileged instructions.

{| class="wikitable"
|+ Window Addressing
|-
! Register group !! Mnemonic !! Register address || Availability
|-
| global || G0...G7 || R[{{0}}0]...R[{{0}}7] || always the same ones, G0 being zero always
|-
| out || O0...O7 || R[{{0}}8]...R[15] || to be handed over to, and returned from, the called subroutine, as its "in"
|-
| local || L0...L7 || R[16]...R[23] || truly local to the current subroutine
|-
| in || I0...I7 || R[24]...R[31] || handed over from the caller, and returned to the caller, as its "out"
|}

SPARC registers are shown in the figure above.

There is also a non-windowed Y register, used by the multiply-step, integer multiply, and integer divide instructions.<ref name="sparc-v8-whitepaper" />{{rp|page=32}}

A SPARC V8 processor with an FPU includes 32 32-bit floating-point registers, each of which can hold one single-precision [[IEEE 754]] floating-point number.  An even–odd pair of floating-point registers can hold one double-precision IEEE 754 floating-point number, and a quad-aligned group of four floating-point registers can hold one quad-precision IEEE 754 floating-point number.<ref name="sparc-v8-whitepaper" />{{rp|page=10}}

A SPARC V9 processor with an FPU includes:<ref name="sparc-v9-whitepaper" />{{rp|pages=36{{hyp}}40}}

* 32 32-bit floating-point registers, each of which can hold one single-precision IEEE 754 floating-point number;
* 32 64-bit floating-point registers, each of which can hold one double-precision IEEE 754 floating-point number;
* 16 128-bit floating-point registers, each of which can hold one quad-precision IEEE 754 floating-point number.

The registers are organized as a set of 64 32-bit registers, with the first 32 being used as the 32-bit floating-point registers, even–odd pairs of all 64 registers being used as the 64-bit floating-point registers, and quad-aligned groups of four floating-point registers being used as the 128-bit floating-point registers.

Floating-point registers are not windowed; they are all global registers.<ref name="sparc-v9-whitepaper" />{{rp|pages=36{{hyp}}40}}