Editing Phase-locked loop (section)

==Structure and function==
Phase-locked loop mechanisms may be implemented as either analog or digital circuits. Both implementations use the same basic structure.
<!--Incomplete block diagram is misleading. Removing until it can be fixed. See [[Talk:Phase-locked loop#Figure_needs_work.2C_I_think]]. [[File:SimplePLL.svg|right|thumb|Block diagram of a PLL (without filter or phase detector, both essential to the operation)]]-->

Analog PLL circuits include four basic elements:
* [[Phase detector]]
* [[Low-pass filter]]
* [[Voltage controlled oscillator]]
* [[Feedback]] path, which may include a [[frequency divider]]

===Variations===
There are several variations of PLLs. Some terms that are used are "analog phase-locked loop" (APLL), also referred to as a linear phase-locked loop" (LPLL), "digital phase-locked loop" (DPLL), "all digital phase-locked loop" (ADPLL), and "software phase-locked loop" (SPLL).<ref name="Best 2007">{{cite book |author=Roland E. Best |title=Phase Locked Loops 6/e : Design, Simulation, and Applications: Design, Simulation, and Applications |edition= |publisher=McGraw Hill Professional |year=2007 |isbn=978-0-07-149375-8}}</ref>

; Analog or linear PLL (APLL):Phase detector is an [[analog multiplier]]. Loop filter is [[Active filter|active]] or [[Passive filter|passive]]. Uses a [[voltage-controlled oscillator]] (VCO). APLL is said to be a ''type II'' if its loop filter has [[transfer function]] with exactly one pole at the origin (see also [[William F. Egan|Egan's conjecture on the pull-in range of type II APLL]]).
; Digital PLL (DPLL): An analog PLL with a digital phase detector (such as [[XOR gate|XOR]], edge-triggered [[JK flip flop]], phase frequency detector). May have digital divider in the loop.
; All digital PLL (ADPLL): Phase detector, filter and oscillator are digital. Uses a [[numerically controlled oscillator]] (NCO).
; Neuronal PLL (NPLL): Phase detector is implemented by neuronal non-linearity, oscillator by rate-controlled oscillating neurons.<ref name="ahipatent2003">Ahissar, E. Neuronal phase-locked loops. U.S. Patent No. 6,581,046 (2003).</ref>
; Software PLL (SPLL): Functional blocks are implemented by software rather than specialized hardware.
; [[Charge-pump phase-locked loop|Charge-pump PLL (CP-PLL)]]:CP-PLL is a modification of phase-locked loops with phase-frequency detector and square waveform signals. See also [[Floyd M. Gardner#Gardner's conjecture on charge-pump phase-locked loops|Gardner's conjecture on CP-PLL]].

===Performance parameters===
{{main|Phase-locked loop ranges}}
*Type and order.
*[[Pll ranges|Frequency ranges]]: hold-in range (tracking range), pull-in range (capture range, acquisition range), lock-in range.<ref name=Leonov2015>{{cite journal | last1=Leonov | first1=G. A. | last2=Kuznetsov | first2=N. V. | last3=Yuldashev | first3=M. V. | last4=Yuldashev | first4=R. V. | title=Hold-in, pull-in, and lock-in ranges of PLL circuits: rigorous mathematical definitions and limitations of classical theory. | journal=IEEE Transactions on Circuits and Systems I: Regular Papers | publisher=IEEE | volume=62 | issue=10 | pages=2454–2464 | doi=10.1109/TCSI.2015.2476295 |arxiv=1505.04262 | year=2015 | s2cid=12292968 }}</ref> See also [[Floyd M. Gardner#Gardner's problem on the lock-in range|Gardner's problem on the lock-in range]], [[William F. Egan#Egan's conjecture on the pull-in range of type II APLL|Egan's conjecture on the pull-in range of type II APLL]], [[Andrew Viterbi#Viterbi's problem on the coincidence of PLL ranges|Viterbi's problem on the PLL ranges coincidence]].
*Loop bandwidth: Defining the speed of the control loop.
*Transient response: Like overshoot and settling time to a certain accuracy (like 50 ppm).
*Steady-state errors: Like remaining phase or timing error.
*Output spectrum purity: Like sidebands generated from a certain VCO tuning voltage ripple.
*Phase-noise: Defined by noise energy in a certain frequency band (like 10&nbsp;kHz offset from carrier). Highly dependent on VCO phase-noise, PLL bandwidth, etc.
*General parameters: Such as power consumption, supply voltage range, output amplitude, etc.