Editing Pentium (original) (section)

===Improvements over the i486===
The P5 microarchitecture brings several important advances over the prior i486 architecture.

* ''Performance'':
** [[Superscalar]] architecture – The Pentium has two datapaths (pipelines) that allow it to complete two instructions per clock cycle in many cases. The main pipe (U) can handle any instruction, while the other (V) can handle the most common simple instructions. Some{{who|date=July 2018}} [[reduced instruction set computer]] (RISC) proponents had argued that the "complicated" x86 instruction set would probably never be implemented by a tightly pipelined [[microarchitecture]], much less by a dual-pipeline design. The 486 and the Pentium demonstrated that this was indeed possible and feasible.
** [[64-bit]] external databus doubles the amount of information possible to read or write on each memory access and therefore allows the Pentium to load its code cache faster than the 80486; it also allows faster access and storage of 64-bit and 80-bit [[x87]] [[Floating-point unit|FPU]] data.
** Separation of code and data caches lessens the fetch and operand read/write conflicts compared to the 486. To reduce access time and implementation cost, both of them are [[Set-associative|2-way associative]], instead of the single 4-way cache of the 486. A related enhancement in the Pentium is the ability to read a contiguous block from the code cache even when it is split between two cache lines (at least 17 bytes in worst case).
** Much faster [[floating-point unit]]. Some instructions showed an enormous improvement, most notably FMUL, with up to 15 times higher throughput than in the 80486 FPU. The Pentium is also able to execute a FXCH ST(x) instruction in parallel with an ordinary (arithmetical or load/store) FPU instruction.
** Four-input address adders enables the Pentium to further reduce the address calculation latency compared to the 80486. The Pentium can calculate full addressing modes with ''segment-base'' + ''base-register'' + ''scaled register'' + ''immediate offset'' in a single cycle; the 486 has a three-input address adder only, and must therefore divide such calculations between two cycles.
** The [[microcode]] can employ both pipelines to enable auto-repeating instructions such as REP MOVSW perform one iteration every clock cycle, while the [[80486]] needed three clocks per iteration (and the earliest x86 chips significantly more than the 486). Also, optimization of the access to the first microcode words during the decode stages helps in making several frequent instructions execute significantly more quickly, especially in their most common forms and in typical cases. Some examples are (486→Pentium, in clock cycles): CALL (3→1), RET (5→2), shifts/rotates (2–3→1).
** A faster, fully hardware-based multiplier makes instructions such as MUL and IMUL several times faster (and more predictable) than in the 80486; the execution time is reduced from 13 to 42 clock cycles down to 10–11 for 32-bit operands.
** Virtualized interrupt to speed up [[virtual 8086 mode]].
** Branch prediction
* ''Other features'':
** Enhanced debug features with the introduction of the Processor-based debug port (see ''Pentium Processor Debugging'' in the Developers Manual, Vol 1).
** Enhanced self-test features like the L1 cache parity check (see ''Cache Structure'' in the Developers Manual, Vol 1).
** New instructions: CPUID, CMPXCHG8B, RDTSC, RDMSR, WRMSR, RSM.
** Test registers TR0–TR7 and MOV instructions for access to them were eliminated.
* The later Pentium MMX also added the [[MMX (instruction set)|MMX instruction set]], a basic integer ''single instruction, multiple data'' ([[SIMD]]) instruction set extension marketed for use in [[multimedia]] applications. MMX could not be used simultaneously with the [[x87]] FPU instructions because the registers were reused (to allow fast context switches). More important enhancements were the doubling of the instruction and data cache sizes and a few microarchitectural changes for better performance.

The Pentium was designed to execute over 100&nbsp;million [[instructions per second]] (MIPS),<ref>{{cite web |url=http://dede.essortment.com/pcusersguides_rjje.htm |title=PC users guide: General Computer Information |access-date=September 14, 2007 |url-status=dead |archive-url=https://web.archive.org/web/20070728013256/http://dede.essortment.com/pcusersguides_rjje.htm |archive-date=July 28, 2007}}</ref> and the 75&nbsp;MHz model was able to reach 126.5 MIPS in certain benchmarks.<ref>{{cite web|url=http://www.islandnet.com/~kpolsson/micropro/proc1994.htm |title=Chronology of Microprocessors |first=Ken |last=Polsson}}</ref> The Pentium architecture typically offered just under twice the performance of a 486 processor per clock cycle in common benchmarks. The fastest 80486 parts (with slightly improved microarchitecture and 100&nbsp;MHz operation) were almost as powerful as the first-generation Pentiums, and the [[AMD]] [[Am5x86]], which despite its name is actually a 486-class CPU, was roughly equal to the Pentium 75 regarding pure ALU performance.