Editing PDP-11 (section)

== Innovative features ==

=== Instruction set orthogonality ===
{{See also|PDP-11 architecture}}

The PDP–11 processor architecture has a mostly [[orthogonal instruction set]]. For example, instead of instructions such as ''load'' and ''store'', the PDP–11 has a ''move'' instruction for which either operand (source and destination) can be memory or register. There are no specific ''input'' or ''output'' instructions; the PDP–11 uses [[memory-mapped I/O]] and so the same ''move'' instruction is used; orthogonality even enables moving data directly from an input device to an output device. More complex instructions such as ''add'' likewise can have memory, register, input, or output as source or destination.

Most operands can apply any of eight addressing modes to eight registers. The addressing modes provide register, immediate, absolute, relative, deferred (indirect), and indexed addressing, and can specify autoincrementation and autodecrementation of a register by one (byte instructions) or two (word instructions). Use of relative addressing lets a machine-language program be [[position-independent code|position-independent]].

=== No dedicated I/O instructions ===
Early models of the PDP–11 had no dedicated [[bus (computing)|bus]] for [[input/output]], but only a [[system bus]] called the [[Unibus]], as input and output devices were mapped to memory addresses.

An input/output device determined the memory addresses to which it would respond, and specified its own [[interrupt vector]] and [[interrupt priority level|interrupt priority]]. This flexible framework provided by the processor architecture made it unusually easy to invent new bus devices, including devices to control hardware that had not been contemplated when the processor was originally designed. DEC openly published the basic Unibus specifications, even offering prototyping bus interface circuit boards, and encouraging customers to develop their own Unibus-compatible hardware.
[[File:PDP-11-70.JPG|thumb|340x340px|A PDP–11/70 system that included two nine-track tape drives, two disk drives, a high speed line printer, a DECwriter dot-matrix keyboard printing terminal and a cathode ray tube terminal installed in a climate-controlled machine room]]
The Unibus made the PDP–11 suitable for custom peripherals. One of the predecessors of [[Alcatel-Lucent]], the [[Bell Telephone Manufacturing Company]], developed the BTMC DPS-1500 packet-switching ([[X.25]]) network and used PDP–11s in the regional and national network management system, with the Unibus directly connected to the DPS-1500 hardware.

Higher-performance members of the PDP–11 family departed from the single-bus approach. The PDP–11/45 had a dedicated data path within the [[Central processing unit|CPU]], connecting semiconductor memory to the processor, with core memory and I/O devices connected via the Unibus.<ref>{{cite book|url=http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf|title=PDP-11/45 Processor Handbook|publisher=[[Digital Equipment Corporation]]|date=1973|page=15|access-date=2022-10-20|archive-date=2022-10-09|archive-url=https://ghostarchive.org/archive/20221009/http://bitsavers.org/pdf/dec/pdp11/handbooks/PDP1145_Handbook_1973.pdf|url-status=live}}</ref> In the PDP–11/70, this was taken a step further, with the addition of a dedicated interface between disks and tapes and memory, via the [[Massbus]]. Although input/output devices continued to be mapped into memory addresses, some additional programming was necessary to set up the added bus interfaces.

=== Interrupts ===
{{further|PDP-11 architecture#Interrupts}}
The PDP–11 supports hardware [[interrupt]]s at four priority levels. Interrupts are serviced by software service routines, which could specify whether they themselves could be interrupted (achieving interrupt [[Nesting (computing)|nesting]]). The event that causes the interrupt is indicated by the device itself, as it informs the processor of the address of its own interrupt vector.

Interrupt vectors are blocks of two 16-bit words in low kernel address space (which normally corresponded to low physical memory) between 0 and 776. The first word of the interrupt vector contains the address of the interrupt service routine and the second word the value to be loaded into the PSW (priority level) on entry to the service routine.

=== Designed for mass production ===
The PDP–11 was designed for ease of manufacture by semiskilled labor. The dimensions of its pieces were relatively non-critical. It used a [[Wire wrap|wire-wrapped]] [[backplane]].