Editing PCI Express (section)

=== Serial bus ===
{{unreferenced section|date=March 2018}}
The bonded serial [[Bus (computing)|bus]] architecture was chosen over the traditional parallel bus because of the inherent limitations of the latter, including [[half-duplex]] operation, excess signal count, and inherently lower [[Bandwidth (computing)|bandwidth]] due to [[timing skew]]. Timing skew results from separate electrical signals within a parallel interface traveling through conductors of different lengths, on potentially different [[printed circuit board]] (PCB) layers, and at possibly different [[Signal velocity|signal velocities]]. Despite being transmitted simultaneously as a single [[Word (data type)|word]], signals on a parallel interface have different travel duration and arrive at their destinations at different times. When the interface clock period is shorter than the largest time difference between signal arrivals, recovery of the transmitted word is no longer possible. Since timing skew over a parallel bus can amount to a few nanoseconds, the resulting bandwidth limitation is in the range of hundreds of megahertz.

[[File:PCIe vs PCI.gif|thumb|'''Highly simplified''' topologies of the Legacy PCI Shared (Parallel) Interface and the PCIe Serial Point-to-Point Interface<ref name="P7MD8" />]]

A serial interface does not exhibit timing skew because there is only one differential signal in each direction within each lane, and there is no external clock signal since clocking information is [[Clock recovery|embedded]] within the serial signal itself. As such, typical bandwidth limitations on serial signals are in the multi-gigahertz range. PCI Express is one example of the general trend toward replacing parallel buses with serial interconnects; other examples include [[Serial ATA]] (SATA), [[USB]], [[Serial Attached SCSI]] (SAS), [[FireWire]] (IEEE 1394), and [[RapidIO]]. In digital video, examples in common use are [[Digital Visual Interface|DVI]], [[HDMI]], and [[DisplayPort]].

Multichannel serial design increases flexibility with its ability to allocate fewer lanes for slower devices.