Editing Intel 4040 (section)

== Characteristics ==
* Data bus: [[4-bit computing|4-bit]]
* Address bus: 12-bit for ROM (multiplexed onto data bus; addresses took three bus cycles to transmit, same as in the 4004), effectively 13-bit with use of bank-switching commands; effectively 10-bit or 8-bit for RAM (8-bit direct address plus one-of-four, i.e. 2-bit equivalent, bank select; the additional 256 "status" memory locations required use of I/O commands to read or write, from an overall 8-bit address space) 
* Voltage: −15 V DC
* Operating frequency: 500 to 740&nbsp;kHz main clock (2-phase, overlapping); 62500 to 92500 8-clock machine cycles per second, each instruction requiring either one or two machine cycles to read and execute, meaning a rough average of 62&nbsp;[[Instructions per second|kIPS]] at 740&nbsp;kHz with an equal mix.<ref group=Note>This may not be entirely accurate and is based on the 4004 characteristics; some of the added instructions may require additional cycles to execute, especially any external register stacking required for interrupt handling, but it is not made clear in the documentation as to whether this is the case; halt/step are special cases which naturally take potentially many millions of cycles to "execute", but as these essentially occur "outside" of the usual program flow, they don't count for speed calculation.</ref>
* Performance: Claimed execution time of ~850&nbsp;μs to add two 32-bit (8-digit BCD) numbers, or around 1175 such operations per second and about 10 machine cycles per digit pair.<ref group=Note>Likewise, based on claimed 4004 performance; "850&nbsp;μs" is a somewhat rounded-off figure claimed in an early Intel brochure and may not be particularly precise, but the total execution time works out to approximately 79 or 80 machine cycles, which fits neatly with either 10 cycles per digit pair, 9 cycles per pair plus 7 for setup and any necessary post-processing, or 8 per pair plus 15 extra (...etc). The actual instruction mix wasn't specified, so without both source code and a list of instruction execution times it's impossible to be sure. A more efficient addition routine might have been possible on the 4040 vs the 4004, but the extra instructions don't suggest any obvious method for achieving this and appear to be focussed on addressing the earlier chip's more obvious shortcomings, e.g. a lack of interrupts and haltability.</ref>