Editing Intel 4004 (section)

===Mazor joins===
Unknown to Hoff, the Busicom team were extremely interested in his proposal. However, there were a number of specific issues that they were concerned about. One key issue was that certain routines like decimal adjust and keyboard handling would use large amounts of ROM space if implemented as subroutines. Another was that the design did not feature any sort of [[interrupt]], so dealing with real-time events would be difficult. Finally, storing the numbers as 4-bit BCD would require additional memory to store the sign and decimal place.{{sfn|Faggin|Hoff|Mazor|Shima|1996|p=13}}

In September 1969, [[Stanley Mazor]] joined Intel from Fairchild. Hoff and Mazor quickly came up with solutions to the Busicom concerns. To address the complexity of the subroutines, originally solved in Busicom's design using one-byte [[macroinstruction]]s and complex decoder circuitry, Mazor developed a 20-byte long [[Interpreter (computing)|interpreter]] that executed the same macroinstructions. Shima suggested adding a new interrupt that would be triggered by a pin, thereby allowing the keyboard to be interrupt-driven. He also modified the Branch Back (return from subroutine) instruction to clear the [[Accumulator (computing)|accumulator]].{{sfn|Faggin|Hoff|Mazor|Shima|1996|p=14}}

To reach the price goals, it was important that the chip be as small as possible and use the fewest number of leads. As data was 4&nbsp;bits and the [[address space]] was 12&nbsp;bits (4096&nbsp;bytes), there was no way direct access could be arranged with anything fewer than about 24&nbsp;pins. This was not small enough, so the design would use a 16-pin [[dual in-line package]] (DIP) layout and use [[multiplexing]] of a single set of 4 lines. This meant specifying which address in ROM to access required three clock cycles, and another two to read it from memory. Running at 1&nbsp;MHz would allow it to perform math on the BCD values at about 80&nbsp;microseconds per digit.{{sfn|Faggin|Hoff|Mazor|Shima|1996|p=15}}

The result of the discussions between Intel and Busicom was an architecture that reduced the 7-chip Busicom design to a 4-chip Intel proposal composed of CPU, ROM, RAM and I/O (input-output) devices. The proposal was presented to a visiting team of Busicom executives in October 1969. They agreed that the new concept was superior and gave Intel the go-ahead to begin development. Hoff was upset to learn that the contract assigned all rights to the design to Busicom, in spite of it being designed entirely within Intel. The team then left for Japan, but Shima remained in California until December, developing many of the subroutines.{{sfn|Faggin|Hoff|Mazor|Shima|1996|p=15}}