Editing IBM 801 (section)

===First implementations===
The initially proposed architecture was a machine with sixteen [[24-bit]] registers and without [[virtual memory]].<ref>{{cite web|url=http://www.bitsavers.org/pdf/ibm/system801/The_801_Minicomputer_an_Overview_Sep76.pdf|title=The 801 Minicomputer - An Overview|date=October 8, 1976|page=9}}</ref><ref>{{cite web|url=http://www.bitsavers.org/pdf/ibm/system801/System_801_Principles_of_Operation_Jan76.pdf|title=System 801 Principles of Operation|date=January 16, 1976}}</ref> It used a two-operand format in the instruction, so that instructions were generally of the form <code>A = A + B</code>, as opposed to the three-operand format, <code>A = B + C</code>. The resulting CPU was operational by the summer of 1980 and was implemented using Motorola MECL-10K discrete component technology{{sfn|Radin|1982}} on large wire-wrapped custom boards. The CPU was clocked at 66&nbsp;ns cycles (approximately 15.15&nbsp;MHz) and could compute at the fast speed of approximately 15&nbsp;[[million instructions per second|MIPS]].

The 801 architecture was used in a variety of IBM devices, including [[channel controller]]s for their S/370 mainframes (such as the [[IBM 3090]]),<ref name="microprocessors-programmers-view">{{cite book |last1=Dewar |first1=Robert B.K. |last2=Smosna |first2=Matthew |title=Microprocessors: A Programmer's View |url=https://archive.org/details/microprocessorsp00robe |url-access=registration |date=1990 |publisher=McGraw-Hill}}</ref>{{rp|377}} various networking devices, and as a [[vertical microcode]] execution unit in the 9373 and 9375 processors of the [[IBM 9370]] mainframe family.{{sfn|Cocke|Markstein|1990|p=9}}<ref name="Mitchell1988">{{cite journal | last1 = Mitchell | first1 = James | title = Implementing a mainframe architecture in a 9370 processor | journal = ACM SIGMICRO Newsletter | date = September 1988 | volume = 19 | issue = 3 | pages = 3–10 | issn = 1050-916X | doi = 10.1145/62185.62186 | pmid = | s2cid = 14602753 | url = }}</ref> The original version of the 801 architecture was the basis for the architecture of the [[IBM ROMP]] [[microprocessor]]<ref name="microprocessors-programmers-view"/>{{rp|378}} used in the [[IBM RT PC]] [[workstation computer]] and several experimental computers from [[IBM Research]]. A derivative of the 801 architecture with [[32-bit]] addressing named ''Iliad'' was intended to serve as the primary processor of the unsuccessful [[IBM AS/400#Fort Knox|Fort Knox]] midrange system project.<ref name="inside-as400">{{cite book|title=Inside the AS/400, Second Edition|url=https://books.google.com/books?id=5DoPAAAACAAJ|isbn=978-1882419661|author=Frank G. Soltis|year=1997|publisher=Duke Press}}</ref>