Editing EEPROM (section)

=={{anchor|FLOTOX}}Theoretical basis of FLOTOX structure==

As is described in former section, old EEPROMs are based on [[avalanche breakdown]]-based [[hot-carrier injection]] with high [[breakdown voltage|reverse breakdown voltage]]. But ''FLOTOX'' theoretical basis is [[Field electron emission#Fowler–Nordheim tunneling|Fowler–Nordheim tunneling]] [[hot-carrier injection]] through a thin [[silicon dioxide]] layer between the [[Floating-gate MOSFET|floating gate]] and the wafer. In other words, it uses a [[tunnel junction]].<ref name="Gutmann-2001">
{{cite journal |last1=Gutmann |first1=Peter |title=Data Remanence in Semiconductor Devices |journal=10th USENIX SECURITY SYMPOSIUM |date=2001-08-15 |pages=39–54 |url=http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/#_Ref513619292 |publisher=IBM T. J. Watson Research Center |url-status=live |archive-url=https://web.archive.org/web/20161012131700/http://static.usenix.org/legacy/events/sec01/full_papers/gutmann/gutmann_html/#_Ref513619292 |archive-date=2016-10-12}}
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Theoretical basis of the physical phenomenon itself is the same as today's [[flash memory]]. But each FLOTOX structure is in conjunction with another read-control transistor because the floating gate itself is just programming and erasing one data bit.<ref>
{{cite web |last1=Janwadkar |first1=Sudhanshu |title=Fabrication of Floating Gate MOS (FLOTOX) |url=https://www.slideshare.net/shudhanshu29/fabrication-of-floating-gate-mos-flotox |website=www.slideshare.net |date=2017-10-24}}
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Intel's FLOTOX device structure improved EEPROM reliability, in other words, the endurance of the write and erase cycles, and the data retention period. A material of study for [[single-event upset|single-event effect]] about FLOTOX is available.<ref>
{{cite web |last1=Koga |first1=R. |last2=Tran |first2=V. |last3=George |first3=J. |last4=Crawford |first4=K. |last5=Crain |first5=S. |last6=Zakrzewski |first6=M. |last7=Yu |first7=P. |title=SEE Sensitivities of Selected Advanced Flash and First-In-First-Out Memories |url=http://www.ti.com/pdfs/hirel/space/V3690SEE.pdf |publisher=The Aerospace Corporation |url-status=live |archive-url=https://web.archive.org/web/20180314042641/http://www.ti.com/pdfs/hirel/space/V3690SEE.pdf |archive-date=2018-03-14}}
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Today, an academic explanation of the FLOTOX device structure can be found in several sources.<ref>{{cite book |last1=Fuller |first1=Dr. Lynn |title=CMOS Process Variations EEPROM Fabrication Technology |date=2012-02-22 |publisher=Microelectronic Engineering, Rochester Institute of Technology |url=https://people.rit.edu/lffeee/EEPROM }}{{Dead link|date=September 2024 |bot=InternetArchiveBot |fix-attempted=yes }}</ref><ref>
{{cite book |last1=Groeseneken |first1=G. |last2=Maes |first2=H. E. |last3=VanHoudt |first3=J. |last4=Witters |first4=J. S. |title=Basics of Nonvolatile Semiconductor Memory Devices |citeseerx=10.1.1.111.9431}}</ref><ref>
{{cite web |last1=Bergemont |first1=Albert |last2=Chi |first2=Min-Hwa |title=US Patent 5856222: Method of fabricating a high density EEPROM cell |url=https://patents.google.com/patent/US5856222A/en |website=patents.google.com |publisher=National Semiconductor Corp. |date=1997-05-05}}
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