Editing Direct memory access (section)

== Modes of operation==

=== Burst mode ===
In ''burst mode'', an entire block of data is transferred in one contiguous sequence. Once the DMA controller is granted access to the system bus by the CPU, it transfers all bytes of data in the data block before releasing control of the system buses back to the CPU,  but renders the CPU inactive for relatively long periods of time. The mode is also called "Block Transfer Mode".

=== Cycle stealing mode ===
The ''[[cycle stealing]] mode'' is used in systems in which the CPU should not be disabled for the length of time needed for burst transfer modes. In the cycle stealing mode, the DMA controller obtains access to the system bus the same way as in burst mode, using ''BR ([[Bus Request]])'' and ''BG ([[Bus Grant]])'' signals, which are the two signals controlling the interface between the CPU and the DMA controller. However, in cycle stealing mode, after one unit of data transfer, the control of the system bus is deasserted to the CPU via BG. It is then continually requested again via BR, transferring one unit of data per request, until the entire block of data has been transferred.<ref>{{cite book |title=Computer Architecture and Organization |last=Hayes |first=John.P |isbn=0-07-027363-4 |year=1978 |page=426-427 |publisher=McGraw-Hill International Book Company }}</ref> By continually obtaining and releasing the control of the system bus, the DMA controller essentially interleaves instruction and data transfers. The CPU processes an instruction, then the DMA controller transfers one data value, and so on. Data is not transferred as quickly, but CPU is not idled for as long as in burst mode. Cycle stealing mode is useful for controllers that monitor data in real time.

=== Transparent mode ===
Transparent mode takes the most time to transfer a block of data, yet it is also the most efficient mode in terms of overall system performance. In transparent mode, the DMA controller transfers data only when the CPU is performing operations that do not use the system buses. The primary advantage of transparent mode is that the CPU never stops executing its programs and the DMA transfer is free in terms of time, while the disadvantage is that the hardware needs to determine when the CPU is not using the system buses, which can be complex. This is also called "''Hidden DMA data transfer mode''".