Editing Charge-coupled device (section)

==Detailed physics of operation==

[[Image:CCD_SONY_ICX493AQA_sensor_side.jpg|thumb|right|[[Sony#Semiconductor and components|Sony]] ICX493AQA 10.14-megapixel APS-C (23.4 × 15.6 mm) CCD from digital camera [[Sony α]] [[DSLR-A200]] or [[DSLR-A300]], sensor side]]

=== Charge generation ===
Before the MOS capacitors are exposed to light, they are [[biasing|biased]] into the depletion region; in n-channel CCDs, the silicon under the bias gate is slightly ''p''-doped or intrinsic. The gate is then biased at a positive potential, above the threshold for strong inversion, which will eventually result in the creation of an ''n'' channel below the gate as in a [[MOSFET]]. However, it takes time to reach this thermal equilibrium: up to hours in high-end scientific cameras cooled at low temperature.<ref>For instance, the specsheet of PI/Acton's [http://www.princetoninstruments.com/Uploads/Princeton/Documents/Datasheets/Princeton_Instruments_SPEC-10_2K_eXcelon_rev_N3_9.22.2011.pdf SPEC-10 camera] specifies a dark current of 0.3 electron per pixel per hour at {{convert|-110|°C|°F|abbr=on}}.</ref> Initially after biasing, the holes are pushed far into the substrate, and no mobile electrons are at or near the surface; the CCD thus operates in a non-equilibrium state called deep depletion.<ref name=sze>{{cite book
 | last1 = Sze
 | first1 = S. M.
 | last2 = Ng
 | first2 = Kwok K.
 | author-link = Simon Sze
 | title = Physics of semiconductor devices
 | publisher = [[John Wiley and Sons]]
 | edition = 3
 | year = 2007
 | isbn = 978-0-471-14323-9
}} Chapter 13.6.</ref>
Then, when [[electron–hole pair]]s are generated in the depletion region, they are separated by the electric field, the electrons move toward the surface, and the holes move toward the substrate. Four pair-generation processes can be identified:
* photo-generation (up to 95% of [[quantum efficiency]]),
* generation in the depletion region,
* generation at the surface, and
* generation in the neutral bulk.

The last three processes are known as dark-current generation, and add noise to the image; they can limit the total usable integration time. The accumulation of electrons at or near the surface can proceed either until image integration is over and charge begins to be transferred, or thermal equilibrium is reached. In this case, the well is said to be full. The maximum capacity of each well is known as the well depth,<ref>{{Cite web |date=March 29, 2001 |title=Pixel Binning |url=http://www.ccd.com/ccd103.html |url-status=dead |archive-url=https://web.archive.org/web/20020605105409/http://www.ccd.com/ccd103.html |archive-date=Jun 5, 2002 |website=Apogee Instruments}}</ref> typically about 10<sup>5</sup> electrons per pixel.<ref name=sze /> CCDs are normally susceptible to ionizing radiation and energetic particles which causes noise in the output of the CCD, and this must be taken into consideration in satellites using CCDs.<ref>{{cite book |doi-access=free | doi=10.1117/12.2309026 | chapter=Radiation effects on image sensors | title=International Conference on Space Optics — ICSO 2012 | date=2017 | editor-last1=Cugny | editor-last2=Karafolas | editor-last3=Armandillo | editor-first1=Bruno | editor-first2=Nikos | editor-first3=Errico | last1=Auvergne | first1=Michel | last2=Ecoffet | first2=Robert | last3=Bardoux | first3=Alain | last4=Gilard | first4=Olivier | last5=Penquer | first5=Antoine | page=12 | isbn=978-1-5106-1617-2 |publisher=SPIE Digital Library }}</ref><ref>{{Cite web |last1=Marshall |first1=Cheryl J. |last2=Marshall |first2=Paul W. |date=6 October 2003 |title=CCD Radiation Effects and Test Issues for Satellite Designers (Review Draft 1.0) |url=https://radhome.gsfc.nasa.gov/radhome/papers/CCD_Lessons_Learned.pdf |url-status=live |archive-url=https://web.archive.org/web/20240214005433/https://radhome.gsfc.nasa.gov/radhome/papers/CCD_Lessons_Learned.pdf |archive-date=Feb 14, 2024 |website=NASA/GSFC Radiation Effects & Analysis}}</ref>

=== Design and manufacturing ===
The photoactive region of a CCD is, generally, an [[epitaxial]] layer of [[silicon]]. It is lightly ''p'' doped (usually with [[boron]]) and is grown upon a [[substrate (materials science)|substrate]] material, often p++. In buried-channel devices, the type of design utilized in most modern CCDs, certain areas of the surface of the silicon are [[ion implantation|ion implanted]] with [[phosphorus]], giving them an n-doped designation. This region defines the channel in which the photogenerated charge packets will travel. [[Simon Sze]] details the advantages of a buried-channel device:<ref name=sze />
<blockquote>This thin layer (= 0.2–0.3 micron) is fully depleted and the accumulated photogenerated charge is kept away from the surface. This structure has the advantages of higher transfer efficiency and lower dark current, from reduced surface recombination. The penalty is smaller charge capacity, by a factor of 2–3 compared to the surface-channel CCD.</blockquote> The gate oxide, i.e. the [[capacitor]] [[dielectric]], is grown on top of the epitaxial layer and substrate.

Later in the process, [[polysilicon]] gates are deposited by [[chemical vapor deposition]], patterned with [[photolithography]], and etched in such a way that the separately phased gates lie perpendicular to the channels. The channels are further defined by utilization of the [[LOCOS]] process to produce the [[channel stop]] region.

Channel stops are thermally grown [[oxide]]s that serve to isolate the charge packets in one column from those in another. These channel stops are produced before the polysilicon gates are, as the LOCOS process utilizes a high-temperature step that would destroy the gate material. The channel stops are parallel to, and exclusive of, the channel, or "charge carrying", regions.

Channel stops often have a p+ doped region underlying them, providing a further barrier to the electrons in the charge packets (this discussion of the physics of CCD devices assumes an [[electron]] transfer device, though hole transfer is possible).

The clocking of the gates, alternately high and low, will forward and reverse bias the diode that is provided by the buried channel (n-doped) and the epitaxial layer (p-doped). This will cause the CCD to deplete, near the [[p–n junction]] and will collect and move the charge packets beneath the gates—and within the channels—of the device.

CCD manufacturing and operation can be optimized for different uses. The above process describes a frame transfer CCD. While CCDs may be manufactured on a heavily doped p++ wafer it is also possible to manufacture a device inside p-wells that have been placed on an n-wafer. This second method, reportedly, reduces smear, [[dark current (physics)|dark current]], and [[infrared]] and red response. This method of manufacture is used in the construction of interline-transfer devices.

Another version of CCD is called a peristaltic CCD. In a peristaltic charge-coupled device, the charge-packet transfer operation is analogous to the peristaltic contraction and dilation of the [[digestive system]]. The peristaltic CCD has an additional implant that keeps the charge away from the silicon/[[silicon dioxide]] interface and generates a large lateral electric field from one gate to the next. This provides an additional driving force to aid in transfer of the charge packets.