Editing AltiVec (section)

=== VSX (Vector Scalar Extension) ===
[[Power ISA#Power ISA v.2.06|Power ISA v2.06]] introduced VSX vector-scalar instructions<ref name="vsx">{{cite web
	|title=Workload acceleration with the IBM POWER vector-scalar architecture
	|publisher=IBM
	|date=2016-03-01
	|url=https://www.researchgate.net/publication/299472451
	|access-date=2017-05-02
	|archive-date=2022-01-25
	|archive-url=https://web.archive.org/web/20220125060920/https://www.researchgate.net/publication/299472451_Workload_acceleration_with_the_IBM_POWER_vector-scalar_architecture
	|url-status=live
	}}</ref> which extend SIMD processing for the Power ISA to support up to 64 registers, with support for regular floating point, decimal floating point and vector execution. [[POWER7]] is the first Power ISA processor to implement Power ISA v2.06.

New instructions are introduced by IBM under the Vector Media Extension category for integer operations as part of the VSX extension in Power ISA 2.07.

New integer vector instructions were introduced by IBM following the VMX encodings as part of the VSX extension in  Power ISA v3.0. Shall be introduced with [[POWER9]] processors.<ref>{{Cite web | url=https://sourceware.org/ml/binutils/2015-11/msg00071.html | title=Peter Bergner - &#91;PATCH, COMMITTED&#93; Add full Power ISA 3.0 / POWER9 binutils support | access-date=2016-12-24 | archive-date=2016-03-07 | archive-url=https://web.archive.org/web/20160307013258/https://sourceware.org/ml/binutils/2015-11/msg00071.html | url-status=live }}</ref>