Editing ARM architecture family (section)

===Design concepts===
The original [[Berkeley RISC]] designs were in some sense teaching systems, not designed specifically for outright performance. To the RISC's basic register-heavy and load/store concepts, ARM added a number of the well-received design notes of the 6502. Primary among them was the ability to quickly serve [[interrupt]]s, which allowed the machines to offer reasonable [[input/output]] performance with no added external hardware. To offer interrupts with similar performance as the 6502, the ARM design limited its physical [[address space]] to 64&nbsp;MB of total addressable space, requiring 26 bits of address. As instructions were 4 bytes (32 bits) long, and required to be aligned on 4-byte boundaries, the lower 2 bits of an instruction address were always zero. This meant the [[program counter]] (PC) only needed to be 24 bits, allowing it to be stored along with the eight bit [[processor flag]]s in a single 32-bit register. That meant that upon receiving an interrupt, the entire machine state could be saved in a single operation, whereas had the PC been a full 32-bit value, it would require separate operations to store the PC and the status flags. This decision halved the interrupt overhead.{{sfn|Evans|2019|loc=23:30}}

Another change, and among the most important in terms of practical real-world performance, was the modification of the [[instruction set]] to take advantage of [[page mode DRAM]]. Recently introduced, page mode allowed subsequent accesses of memory to run twice as fast if they were roughly in the same location, or "page", in the DRAM chip. Berkeley's design did not consider page mode and treated all memory equally. The ARM design added special vector-like memory access instructions, the "S-cycles", that could be used to fill or save multiple registers in a single page using page mode. This doubled memory performance when they could be used, and was especially important for graphics performance.{{sfn|Evans|2019|loc=26:00}}

The Berkeley RISC designs used [[register window]]s to reduce the number of register saves and restores performed in [[procedure call]]s; the ARM design did not adopt this.

Wilson developed the instruction set, writing a simulation of the processor in [[BBC&nbsp;BASIC]] that ran on a BBC Micro with a [[BBC Micro expansion unit#6502 Second Processor|second 6502 processor]].<ref>{{cite web |title=ARM Instruction Set design history with Sophie Wilson (Part 3) |url=https://www.youtube.com/watch?v=QqxThgLTLyk&t=960 |url-status=live |archive-url=https://ghostarchive.org/varchive/youtube/20211211/QqxThgLTLyk |archive-date=2021-12-11 |via=YouTube |date=10 May 2015 |access-date=25 May 2020}}{{cbignore}}</ref><ref>{{cite web |title=Oral History of Sophie Wilson – 2012 Computer History Museum Fellow |url=http://archive.computerhistory.org/resources/access/text/2012/06/102746190-05-01-acc.pdf |work=Computer History Museum |date=31 January 2012 |access-date=25 May 2020}}</ref> This convinced Acorn engineers they were on the right track. Wilson approached Acorn's CEO, [[Hermann Hauser]], and requested more resources. Hauser gave his approval and assembled a small team to design the actual processor based on Wilson's ISA.<ref>{{cite journal |last=Harker |first=T. |date=Summer 2009 |title=ARM gets serious about IP (Second in a two-part series [Associated Editors' View] |url=https://ieeexplore.ieee.org/document/5191430 |journal=IEEE Solid-State Circuits Magazine |volume=1 |issue=3 |pages=8–69 |doi=10.1109/MSSC.2009.933674 |s2cid=36567166 |issn=1943-0590}}</ref> The official Acorn RISC Machine project started in October 1983.