Editing Peripheral Component Interconnect (section)

===Cache snooping (obsolete)===
PCI originally included optional support for [[write-back]] [[cache coherence]].  This required support by cacheable memory targets, which would listen to two pins from the cache on the bus, SDONE (snoop done) and SBO# (snoop backoff).<ref name=pci21>PCI Local Bus Specification, revision 2.1</ref>

Because this was rarely implemented in practice, it was deleted from revision 2.2 of the PCI specification,<ref name="pci30"/><ref name=pci22>{{cite book|title=PCI Local Bus Specification Revision 2.2 |date=December 18, 1998 |author=<!--Staff writer(s); no by-line.-->|publisher=[[PCI-SIG|PCI Special Interest Group]]|location=[[Hillsboro, Oregon]]}}</ref> and the pins re-used for [[SMBus]] access in revision 2.3.<ref name=pci23/>

The cache would watch all memory accesses, without asserting DEVSEL#.  If it noticed an access that might be cached, it would drive SDONE low (snoop not done).  A coherence-supporting target would avoid completing a data phase (asserting TRDY#) until it observed SDONE high.

In the case of a write to data that was clean in the cache, the cache would only have to invalidate its copy and would assert SDONE as soon as this was established.  However, if the cache contained dirty data, the cache would have to write it back before the access could proceed. so it would assert SBO# when raising SDONE.  This would signal the active target to assert STOP# rather than TRDY#, causing the initiator to disconnect and retry the operation later.  In the meantime, the cache would arbitrate for the bus and write its data back to memory.

Targets supporting cache coherency are also required to terminate bursts before they cross cache lines.