Editing Peripheral Component Interconnect (section)

===64-bit PCI===
{{Hatnote|This section explains only basic 64-bit PCI; the full [[PCI-X]] protocol extension is much more extensive.}}
Starting from revision 2.1,{{clarify|date=October 2020}} the PCI specification includes optional 64-bit support.  This is provided via an extended connector which provides the 64-bit bus extensions AD[63:32], C/BE[7:4]#, and PAR64, and a number of additional power and ground pins. The 64-bit PCI connector can be distinguished from a 32-bit connector by the additional 64-bit segment.

Memory transactions between 64-bit devices may use all 64&nbsp;bits to double the data transfer rate.  Non-memory transactions (including configuration and I/O space accesses) may not use the 64-bit extension.  During a 64-bit burst, burst addressing works just as in a 32-bit transfer, but the address is incremented twice per data phase.  The starting address must be 64-bit aligned; i.e. AD2 must be 0.  The data corresponding to the intervening addresses (with AD2 = 1) is carried on the upper half of the AD bus.

To initiate a 64-bit transaction, the initiator drives the starting address on the AD bus and asserts REQ64# at the same time as FRAME#.  If the selected target can support a 64-bit transfer for this transaction, it replies by asserting ACK64# at the same time as DEVSEL#.  A target may decide on a per-transaction basis whether to allow a 64-bit transfer.

If REQ64# is asserted during the address phase, the initiator also drives the high 32 bits of the address and a copy of the bus command on the high half of the bus.  If the address requires 64 bits, a dual address cycle is still required, but the high half of the bus carries the upper half of the address and the final command code during both address phase cycles; this allows a 64-bit target to see the entire address and begin responding earlier.

If the initiator sees DEVSEL# asserted without ACK64#, it performs 32-bit data phases.  The data which would have been transferred on the upper half of the bus during the first data phase is instead transferred during the second data phase.  Typically, the initiator drives all 64 bits of data before seeing DEVSEL#.  If ACK64# is missing, it may cease driving the upper half of the data bus.

The REQ64# and ACK64# lines are held asserted for the entire transaction save the last data phase and deasserted at the same time as FRAME# and DEVSEL#, respectively.

The PAR64 line operates just like the PAR line, but provides even parity over AD[63:32] and C/BE[7:4]#.  It is only valid for address phases if REQ64# is asserted.  PAR64 is only valid for data phases if both REQ64# and ACK64# are asserted.