Editing PCI Express (section)

==== Data transmission ====
PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to conventional PCI, which has dedicated interrupt lines. When the problem of IRQ sharing of pin based interrupts is taken into account and the fact that message signaled interrupts (MSI) can bypass an I/O APIC and be delivered to the CPU directly, MSI performance ends up being substantially better.<ref name="vV4Hv" />

Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as ''data striping''. While requiring significant hardware complexity to synchronize (or [[clock skew|deskew]]) the incoming striped data, striping can significantly reduce the latency of the ''n''th byte on a link. While the lanes are not tightly synchronized, there is a limit to the ''lane to lane skew'' of 20/8/6&nbsp;ns for 2.5/5/8&nbsp;GT/s so the hardware buffers can re-align the striped data.<ref name="iPAaS" /> Due to padding requirements, striping may not necessarily reduce the latency of small data packets on a link.

As with other high data rate serial transmission protocols, the clock is [[self-clocking signal|embedded]] in the signal. At the physical level, PCI Express 2.0 utilizes the [[8b/10b encoding]] scheme<ref name="faq3" /> (line code) to ensure that strings of consecutive identical digits (zeros or ones) are limited in length. This coding was used to prevent the receiver from losing track of where the bit edges are. In this coding scheme every eight (uncoded) payload bits of data are replaced with 10 (encoded) bits of transmit data, causing a 20% overhead in the electrical bandwidth. To improve the available bandwidth, PCI Express version 3.0 instead uses [[64b/66b encoding|128b/130b]] encoding (1.54% overhead). [[Line encoding]] limits the run length of identical-digit strings in data streams and ensures the receiver stays synchronised to the transmitter via [[clock recovery]].

A desirable balance (and therefore [[spectral density]]) of 0 and 1 bits in the data stream is achieved by [[XOR]]ing a known [[Linear-feedback shift register|binary polynomial]] as a "[[scrambler]]" to the data stream in a feedback topology. Because the scrambling polynomial is known, the data can be recovered by applying the XOR a second time. Both the scrambling and descrambling steps are carried out in hardware.

Dual simplex in PCIe means there are two simplex channels on every PCIe lane. Simplex means communication is only possible in one direction. By having two simplex channels, two-way communication is made possible. One differential pair is used for each channel.<ref>{{cite web |title=PCIe Data Transmission Overview  |website=[[Microchip Technology]] |url=https://ww1.microchip.com/downloads/aemDocuments/documents/TCG/ProductDocuments/Brochures/00003818.pdf }}</ref><ref name="auto"/><ref>{{cite book | url=https://books.google.com/books?id=k_HJCgAAQBAJ&dq=pcie+differential+pair&pg=PT128 | isbn=978-0-7686-9003-3 | title=CompTIA A+ Exam Cram (Exams 220-602, 220-603, 220-604) | date=19 July 2007 | publisher=Pearson Education }}</ref>