Editing X86 (section)

=== APX (Advanced Performance Extensions) ===
APX (Advanced Performance Extensions) are extensions to double the number of general-purpose registers from 16 to 32 and add new features to improve general-purpose performance.<ref>{{Cite web |last1=Winkel |first1=Sebastian |last2=Agron |first2=Jason |title=Advanced Performance Extensions (APX) |url=https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html |access-date=2023-10-22 |website=[[Intel]] |language=en}}</ref><ref>{{cite web |last1=Robinson |first1=Dan |title=Intel adds fresh x86 and vector instructions for future chips |url=https://www.theregister.com/2023/07/26/intel_x86_vector_instructions/ |website=The Register |access-date=22 October 2023}}</ref><ref>{{cite web |last1=Bonshor |first1=Gavin |title=Intel Unveils AVX10 and APX Instruction Sets: Unifying AVX-512 For Hybrid Architectures |url=https://www.anandtech.com/show/18975/intel-unveils-avx10-and-apx-isas-unifying-avx512-for-hybrid-architectures- |website=AnandTech |access-date=22 October 2023}}</ref><ref>{{cite web |last1=Alcorn |first1=Paul |title=Intel's New AVX10 Brings AVX-512 Capabilities to E-Cores |url=https://www.tomshardware.com/news/intels-new-avx10-brings-avx-512-capabilities-to-e-cores |website=Tom's Hardware |date=July 24, 2023 |access-date=22 October 2023}}</ref> These extensions have been called "generational"<ref>{{cite web |last1=Shah |first1=Agam |title=Intel's Generational On-Chip Change APX Will Make All the Apps Faster |url=https://thenewstack.io/intels-generational-on-chip-change-apx-will-make-all-the-apps-faster/ |website=The New Stack |date=August 9, 2023 |access-date=22 October 2023}}</ref> and "the biggest x86 addition since 64 bits".<ref>{{cite web |last1=Byrne |first1=Joseph |title=APX is Biggest x86 Addition Since 64 Bits |url=https://www.techinsights.com/blog/apx-biggest-x86-addition-64-bits |website=Tech Insights}}</ref> Intel contributed APX support to [[GNU Compiler Collection]] (GCC) 14.<ref>{{cite web |last1=Larabel |first1=Michael |title=Intel APX Code Begins Landing Within The GCC Compiler |url=https://www.phoronix.com/news/GCC-Intel-APX-Starts-Landing |website=Phoronix |access-date=22 October 2023}}</ref>

According to the architecture specification,<ref>{{Cite web |date=2023-07-21 |title=Intel® Advanced Performance Extensions (Intel® APX) Architecture Specification |url=https://www.intel.com/content/www/us/en/content-details/784266/intel-advanced-performance-extensions-intel-apx-architecture-specification.html |access-date=2023-10-22 |website=Intel}}</ref> the main features of APX are:

* 16 additional general-purpose registers, called the Extended GPRs (EGPRs)
* Three-operand instruction formats for many integer instructions
* New conditional instructions for loads, stores, and comparisons with common instructions that do not modify flags
* Optimized register save/restore operations
* A 64-bit absolute direct jump instruction

Extended GPRs for general purpose instructions are encoded using 2-byte [[REX prefix|REX2]] prefix, while new instructions and extended operands for existing [[Advanced Vector Extensions|AVX]]/[[AVX2]]/[[AVX-512]] instructions are encoded with [[EVEX prefix#Extended EVEX prefix|extended EVEX]] prefix which has four variants used for different groups of instructions.