Editing Dynamic random-access memory (section)

====Burst EDO DRAM====
An evolution of EDO DRAM, burst EDO DRAM (BEDO DRAM), could process four memory addresses in one burst, for a maximum of {{nowrap|5-1-1-1}}, saving an additional three clocks over optimally designed EDO memory. It was done by adding an address counter on the chip to keep track of the next address. BEDO also added a pipeline stage allowing page-access cycle to be divided into two parts. During a memory-read operation, the first part accessed the data from the memory array to the output stage (second latch). The second part drove the data bus from this latch at the appropriate logic level. Since the data is already in the output buffer, quicker access time is achieved (up to 50% for large blocks of data) than with traditional EDO.

Although BEDO DRAM showed additional optimization over EDO, by the time it was available the market had made a significant investment towards synchronous DRAM, or SDRAM.<ref>{{cite web|last=Kent |first=Dean |url=https://www.tomshardware.com/reviews/ram-guide,89-7.html |title=Burst EDO (BEDO) - Ram Guide {{pipe}} Tom's Hardware |publisher=Tomshardware.com |date= 24 October 1998|access-date=2022-03-09}}</ref>  Even though BEDO RAM was superior to SDRAM in some ways, the latter technology quickly displaced BEDO.