Editing Peripheral Component Interconnect (section)

===Burst addressing===
For memory space accesses, the words in a burst may be accessed in several orders.  The unnecessary low-order address bits AD[1:0] are used to convey the initiator's requested order.  A target which does not support a particular order must terminate the burst after the first word.  Some of these orders depend on the cache line size, which is configurable on all PCI devices.

{|class=wikitable
|+PCI burst ordering
! A[1] || A[0] || Burst order (with 16-byte cache line)
|-
| 0 || 0 || Linear incrementing (0x0C, 0x10, 0x14, 0x18, 0x1C, ...)
|-
| 0 || 1 || Cacheline toggle (0x0C, 0x08, 0x04, 0x00, 0x1C, 0x18, ...)
|-
| 1 || 0 || Cacheline wrap (0x0C, 0x00, 0x04, 0x08, 0x1C, 0x10, ...)
|-
| 1 || 1 || Reserved (disconnect after first transfer)
|}

If the starting offset within the cache line is zero, all of these modes reduce to the same order.

Cache line toggle and cache line wrap modes are two forms of critical-word-first cache line fetching.  Toggle mode XORs the supplied address with an incrementing counter.  This is the native order for Intel 486 and Pentium processors.  It has the advantage that it is not necessary to know the cache line size to implement it.

PCI version 2.1 obsoleted toggle mode and added the cache line wrap mode,{{r|changes21|p=2}} where fetching proceeds linearly, wrapping around at the end of each cache line.  When one cache line is completely fetched, fetching jumps to the starting offset in the next cache line.

Most PCI devices only support a limited range of typical cache line sizes; if the cache line size is programmed to an unexpected value, they force single-word access.

PCI also supports burst access to I/O and configuration space, but only linear mode is supported.  (This is rarely used, and may be buggy in some devices; they may not support it, but not properly force single-word access either.)