Editing PCI Express (section)

== Extensions and future directions <span class="anchor" id="M-PCIE"></span><span class="anchor" id="Thunderbolt"></span> ==
Some vendors offer PCIe over fiber products,<ref name="PCIeFiber" /><ref name="adnacoPCIe" /><ref name="g6np3" /> with active optical cables (AOC) for PCIe switching at increased distance in PCIe expansion drawers,<ref name="IBM-REDP-5137-00">{{Cite web|url=http://www.redbooks.ibm.com/redpapers/pdfs/redp5137.pdf|title=IBM Power Systems E870 and E880 Technical Overview and Introduction}}</ref><ref name="IBM-REDP-5649-00"/> or in specific cases where transparent PCIe bridging is preferable to using a more mainstream standard (such as [[InfiniBand]] or [[Ethernet]]) that may require additional software to support it.

''[[Thunderbolt (interface)|Thunderbolt]]'' was co-developed by [[Intel]] and [[Apple Inc.|Apple]] as a general-purpose high speed interface combining a logical PCIe link with [[DisplayPort]] and was originally intended as an all-fiber interface, but due to early difficulties in creating a consumer-friendly fiber interconnect, nearly all implementations are copper systems. A notable exception, the [[Sony Vaio Z series|Sony VAIO Z]] VPC-Z2, uses a nonstandard USB port with an optical component to connect to an outboard PCIe display adapter. Apple has been the primary driver of Thunderbolt adoption through 2011, though several other vendors<ref name="kZCuH" /> have announced new products and systems featuring Thunderbolt. Thunderbolt 3 forms the basis of the [[USB4]] standard.

''Mobile PCIe'' specification (abbreviated to ''M-PCIe'') allows PCI Express architecture to operate over the [[MIPI Alliance]]'s [[M-PHY]] physical layer technology. Building on top of already existing widespread adoption of M-PHY and its low-power design, Mobile PCIe lets mobile devices use PCI Express.<ref name="RKmF2" />

=== Draft process ===
There are 5 primary releases/checkpoints in a PCI-SIG specification:<ref name="yT5P8" />
* Draft 0.3 (Concept): this release may have few details, but outlines the general approach and goals.
* Draft 0.5 (First draft): this release has a complete set of architectural requirements and must fully address the goals set out in the 0.3 draft.
* Draft 0.7 (Complete draft): this release must have a complete set of functional requirements and methods defined, and no new functionality may be added to the specification after this release. Before the release of this draft, electrical specifications must have been validated via test silicon.
* Draft 0.9 (Final draft): this release allows PCI-SIG member companies to perform an internal review for intellectual property, and no functional changes are permitted after this draft.
* 1.0 (Final release): this is the final and definitive specification, and any changes or enhancements are through Errata documentation and Engineering Change Notices (ECNs) respectively.

Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources.