Editing PCI Express (section)

=== PCI Express 7.0 <span class="anchor" id="7.0"></span> ===
On 21 June 2022, PCI-SIG announced the development of PCI Express 7.0 specification.<ref>{{cite web|url=https://www.businesswire.com/news/home/20220621005137/en |title=PCI-SIG® Announces PCI Express® 7.0 Specification to Reach 128 GT/s |publisher=Business Wire |date=2022-06-21 |accessdate=2022-06-25}}</ref> It will deliver 128&nbsp;GT/s raw bit rate and up to 242&nbsp;GB/s per direction in x16 configuration, using the same [[Pulse-amplitude modulation|PAM4]] signaling as version 6.0. Doubling of the data rate will be achieved by fine-tuning channel parameters to decrease signal losses and improve power efficiency, but signal integrity is expected to be a challenge. The specification is expected to be finalized in 2025.

On 3 April 2024, the PCI Express 7.0 revision 0.5 specification (a "first draft") was released.<ref name="PCIe70v05"/>

On 17 January 2025, PCI-SIG announced the release of PCIe 7.0 specification version 0.7 (a "complete draft").<ref name="PCIe70v07"/>

On 19 March 2025, PCI-SIG announced the release of PCIe 7.0 specification version 0.9 (a "final draft"); planned final release is still in 2025.<ref name="PCIe70v09"/>

The following main points were formulated as objectives of the new standard:
* Delivering 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration
* Utilizing PAM4 (Pulse Amplitude Modulation with 4 levels) signaling
* Focusing on the channel parameters and reach
* Improving power efficiency
* Continuing to deliver the low-latency and high-reliability targets
* Maintaining backwards compatibility with all previous generations of PCIe technology