Editing Itanium (section)

== Processors ==

=== Released processors ===
[[File:Itanium 2 mx2 module top.jpg|thumb|Itanium 2 mx2 'Hondo' (top)]]
[[File:Itanium 2 mx2 module bottom.jpg|thumb|Itanium 2 mx2 'Hondo' (bottom)]]

The Itanium processors show a progression in capability. Merced was a proof of concept. McKinley dramatically improved the memory hierarchy and allowed Itanium to become reasonably competitive. Madison, with the shift to a 130&nbsp;nm process, allowed for enough cache space to overcome the major performance bottlenecks. Montecito, with a 90&nbsp;nm process, allowed for a dual-core implementation and a major improvement in performance per watt. Montvale added three new features: core-level lockstep, demand-based switching and [[front-side bus]] frequency of up to 667&nbsp;MHz.

{| class="wikitable"
|-
![[List of Intel codenames|Codename]] || process || Released || | Clock || L2 [[CPU cache|Cache]]/<br />core || L3 [[CPU cache|Cache]]/<br />processor || [[Front Side Bus|Bus]] || [[die (integrated circuit)|dies]]/<br />dev. || cores/<br />[[die (integrated circuit)|die]] || [[Thermal design power|TDP]]/<br />dev. || Comments
|-
! colspan="11" style="background:#ffebad;"| Itanium
|-
| rowspan="2" style="vertical-align:top;"|Merced || rowspan="2" |[[180 nanometer|180&nbsp;nm]] || rowspan="2" |2001-05-29 || 733&nbsp;MHz || rowspan="2" | {{0}}96&nbsp;KB || rowspan="2"| 1 MB
2 MB
| rowspan="2" | 266&nbsp;MHz || rowspan="2" | {{0}}1 || rowspan="2" | {{0}}1 || 116 || 2&nbsp;or&nbsp;4&nbsp;MB off-die L3 cache
|-
| 800&nbsp;MHz || 130 || 2&nbsp;or&nbsp;4&nbsp;MB off-die L3 cache
|-
! colspan="11" style="background:#ffebad;"| Itanium 2
|-
| rowspan="3" style="vertical-align:top;"|McKinley || rowspan="3" |[[180 nanometer|180&nbsp;nm]] || rowspan="3" |2002-07-08 || 900&nbsp;MHz || rowspan="19" | 256&nbsp;KB ||rowspan="2" |{{0}}1.5&nbsp;MB || rowspan="13" | 400&nbsp;MHz || rowspan="10" | {{0}}1 || rowspan="10" | {{0}}1 || 90 || rowspan=3 style="vertical-align:top;"| HW branchlong
|-
| rowspan="2" |1&nbsp;GHz ||style='border-style: solid solid none solid;'|100
|-
| {{0}}3&nbsp;MB ||style='border-style: none solid solid solid;|{{zwsp}}
|-
| rowspan="6" style="vertical-align:top;" | Madison || rowspan="16" | [[130 nanometer|130&nbsp;nm]] || rowspan="3" | 2003-06-30 || 1.3&nbsp;GHz || {{0}}3&nbsp;MB || 97 || 
|-
|1.4&nbsp;GHz || {{0}}4&nbsp;MB || 91 || 
|-
|1.5&nbsp;GHz || {{0}}6&nbsp;MB || 107 ||
|-
|2003-09-08 || rowspan="2" |1.4&nbsp;GHz || {{0}}1.5&nbsp;MB || rowspan=2 |91 ||
|-
|rowspan="2" |{{nowrap|2004-04-13}} || rowspan=2 | {{0}}3&nbsp;MB ||&nbsp;
|-
|1.6&nbsp;GHz || 99||
|-
|Deerfield || {{nowrap|2003-09-08}} || 1.0&nbsp;GHz || {{0}}1.5&nbsp;MB || 55 || Low voltage
|-
|Hondo<ref>{{cite news|url=https://www.theregister.com/2004/05/06/hp_mx2_itaniummodule/|title=HP rides Hondo to super-sized Itanium servers|first=Ashlee|last=Vance|author-link=Ashlee Vance|website=[[The Register]]|date=May 6, 2004|access-date=November 25, 2022}}</ref> || {{nowrap|2004-06}} || 1.1&nbsp;GHz || {{0}}4&nbsp;MB || {{0}}2 || {{0}}1 || 170 || Not a product of Intel, but of [[Hewlett-Packard|HP]]. 32&nbsp;MB L4
|-
| rowspan="3" style="vertical-align:top;"|Fanwood || rowspan="6" |{{nowrap|2004-11-08}} || 1.3&nbsp;GHz || rowspan=3| {{0}}3&nbsp;MB || rowspan="8" | {{0}}1 || rowspan="8" | {{0}}1 || 62 ||Low voltage
|-
|rowspan="2" |1.6&nbsp;GHz ||rowspan="2" |99 ||&nbsp;
|-
| 533&nbsp;MHz ||
|-
| rowspan="5" style="vertical-align:top;"|Madison 9M || 1.5&nbsp;GHz || {{0}}4&nbsp;MB || rowspan="3" |400&nbsp;MHz ||rowspan="5" |122||
|-
| rowspan="2" |1.6&nbsp;GHz || {{0}}6&nbsp;MB ||
|-
| {{0}}9&nbsp;MB ||
|-
|rowspan="2" |{{nowrap|2005-07-05}} || rowspan="2" |1.67&nbsp;GHz || {{0}}6&nbsp;MB || rowspan="2" |667&nbsp;MHz ||
|-
| {{0}}9&nbsp;MB ||
|-
! colspan="11" style="background:#ffebad;"| Itanium&nbsp;2 9000 series
|-
| style="vertical-align:top;"|[[Montecito (processor)|Montecito]] || {{0}}[[90 nanometer|90&nbsp;nm]] || {{nowrap|2006-07-18}} || 1.4–<br />1.6&nbsp;GHz || 256&nbsp;KB (D)+<br />1&nbsp;MB (I) || {{0}}6–24&nbsp;MB || 400–<br />533&nbsp;MHz ||{{0}}1 ||{{0}}2 || {{0}}75–104 || style="vertical-align:top;"|Virtualization, Multithread, no HW IA-32
|-
! colspan="11" style="background:#ffebad;"| Itanium 9100 series
|-
|valign="top"|[[Montvale (processor)|Montvale]] || {{0}}[[90 nanometer|90&nbsp;nm]] || {{nowrap|2007-10-31}} || 1.42–<br />1.66&nbsp;GHz || 256&nbsp;KB&nbsp;(D)+<br />1&nbsp;MB (I) || {{0}}8–24&nbsp;MB || 400–<br />667&nbsp;MHz || {{0}}1 || {{0}}1–2 || {{0}}75–104 || valign="top"|Core-level lockstep, demand-based switching
|-
! colspan="11" style="background:#ffebad;"| Itanium 9300 series
|-
|valign="top"|[[Tukwila (processor)|Tukwila]] || {{0}}[[65 nanometer|65&nbsp;nm]] || {{nowrap|2010-02-08}} || 1.33–<br />1.73&nbsp;GHz || 256&nbsp;KB (D)+<br />512&nbsp;KB (I) || 10–24&nbsp;MB || QPI with<br />4.8 [[Transfer (computing)|GT]]/s || {{0}}1 || {{0}}2–4 || 130–185 || valign="top"|A new point-to-point processor interconnect, the [[Intel QuickPath Interconnect|QPI]],<br />replacing the [[Front-side bus|FSB]]. [[Turbo Boost]]
|-
! colspan="11" style="background:#ffebad;"| Itanium 9500 series
|-
|valign="top"|[[Poulson (processor)|Poulson]] || {{0}}[[32 nanometer|32&nbsp;nm]] || {{nowrap|2012-11-08}}<br /><ref>{{cite press release |title=New Intel Itanium Processor 9500 Delivers Breakthrough Capabilities for Mission-Critical Computing |url=http://newsroom.intel.com/community/intel_newsroom/blog/2012/11/08/new-intel-itanium-processor-9500-delivers-breakthrough-capabilities-for-mission-critical-computing |publisher=Intel |access-date=November 9, 2012 |archive-date=November 12, 2012 |archive-url=https://web.archive.org/web/20121112014247/http://newsroom.intel.com/community/intel_newsroom/blog/2012/11/08/new-intel-itanium-processor-9500-delivers-breakthrough-capabilities-for-mission-critical-computing |url-status=dead }}</ref> || 1.73–<br />2.53&nbsp;GHz || 256&nbsp;KB (D)+<br />512&nbsp;KB (I) || 20–32&nbsp;MB || QPI with<br />6.4 [[Transfer (computing)|GT]]/s || {{0}}1 || {{0}}4–8 || 130–170 || valign="top"|Doubled issue width (from 6 to 12 instructions per cycle),<br />Instruction Replay technology, Dual-domain hyperthreading<ref>{{cite web |last=Shilov |first=Anton |title=Intel Launches Eight-Core Itanium 9500 "Poulson" Mission-Critical Server Processor |url=http://www.xbitlabs.com/news/cpu/display/20121108120233_Intel_Launches_Eight_Core_Itanium_9500_Poulson_Mission_Critical_Server_Processor.html |publisher=X-bit Labs |access-date=November 9, 2012 |archive-url=https://web.archive.org/web/20121110213532/http://www.xbitlabs.com/news/cpu/display/20121108120233_Intel_Launches_Eight_Core_Itanium_9500_Poulson_Mission_Critical_Server_Processor.html |archive-date=November 10, 2012 |df=mdy-all |url-status=dead}}</ref><ref name="poulson-the-future-of-itanium-servers" /><ref>{{cite web |last=Undy |first=Steve |title=WHITE PAPER Intel Itanium Processor 9500 Series |url=http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-9500-massive-parallelism-mission-critical-computing-paper.pdf |publisher=Intel |access-date=November 9, 2012 |archive-date=June 16, 2013 |archive-url=https://web.archive.org/web/20130616020413/http://www.intel.com/content/dam/www/public/us/en/documents/white-papers/itanium-9500-massive-parallelism-mission-critical-computing-paper.pdf |url-status=dead }}</ref>
|-
! colspan="11" style="background:#ffebad;"| Itanium 9700 series
|-
|valign="top"|[[Kittson (processor)|Kittson]] || {{0}}[[32 nanometer|32&nbsp;nm]] || {{nowrap|2017-05-11}}<br /><ref name="IA-PCWorld"/> || 1.73–<br />2.66&nbsp;GHz || 256&nbsp;KB (D)+<br />512&nbsp;KB (I) || 20–32&nbsp;MB || QPI with<br />6.4 [[Transfer (computing)|GT]]/s || {{0}}1 || {{0}}4–8 || 130–170 || No architectural improvements over Poulson,<br />5&nbsp;% higher clock for the top model
|-
! Codename || process || Released || | Clock || L2 Cache/<br />core || L3 Cache/<br />processor || Bus || dies/<br />dev. || cores/<br />die || watts/<br />dev. || Comments
|-
! colspan="11" |[[List of Intel Itanium processors]]
|}