Editing Dynamic random-access memory (section)

====Page mode DRAM====
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'''Page mode DRAM''' is a minor modification to the first-generation DRAM IC interface which improves the performance of reads and writes to a row by avoiding the inefficiency of precharging and opening the same row repeatedly to access a different column. In page mode DRAM, after a row is opened by holding {{overline|RAS}} low, the row can be kept open, and multiple reads or writes can be performed to any of the columns in the row. Each column access is initiated by presenting a column address and asserting {{overline|CAS}}. For reads, after a delay (''t''<sub>CAC</sub>), valid data appears on the data out pins, which are held at high-Z before the appearance of valid data. For writes, the write enable signal and write data is presented along with the column address.<ref name="Kenner 13">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=13}}</ref>

Page mode DRAM was in turn later improved with a small modification which further reduced latency. DRAMs with this improvement are called '''fast page mode DRAMs''' ('''FPM DRAMs'''). In page mode DRAM, the chip does not capture the column address until {{overline|CAS}} is asserted, so column access time (until data out was valid) begins when {{overline|CAS}} is asserted.  In FPM DRAM, the column address can be supplied while {{overline|CAS}} is still deasserted, and the main column access time (''t''<sub>AA</sub>) begins as soon as the address is stable.  The {{overline|CAS}} signal is only needed to enable the output (the data out pins were held at high-Z while {{overline|CAS}} was deasserted), so time from {{overline|CAS}} assertion to data valid (''t''<sub>CAC</sub>) is greatly reduced.<ref name="Kenner 14">{{harvnb|Keeth|Baker|Johnson|Lin|2007|p=14}}</ref> Fast page mode DRAM was introduced in 1986 and was used with the [[Intel 80486]].

''Static column'' is a variant of fast page mode in which the column address does not need to be latched, but rather the address inputs may be changed with {{overline|CAS}} held low, and the data output will be updated accordingly a few nanoseconds later.<ref name="Kenner 14" />

''Nibble mode'' is another variant in which four sequential locations within the row can be accessed with four consecutive pulses of {{overline|CAS}}. The difference from normal page mode is that the address inputs are not used for the second through fourth {{overline|CAS}} edges but are generated internally starting with the address supplied for the first {{overline|CAS}} edge.<ref name="Kenner 14" />  The predictable addresses let the chip prepare the data internally and respond very quickly to the subsequent {{overline|CAS}} pulses.