Editing Peripheral Component Interconnect (section)

====Initiator burst termination====
The initiator can mark any data phase as the final one in a transaction by deasserting FRAME# at the same time as it asserts IRDY#.  The cycle after the target asserts TRDY#, the final data transfer is complete, both sides deassert their respective RDY# signals, and the bus is idle again.  The master may not deassert FRAME# before asserting IRDY#, nor may it deassert FRAME# while waiting, with IRDY# asserted, for the target to assert TRDY#.

The only minor exception is a ''master abort termination'', when no target responds with DEVSEL#.  Obviously, it is pointless to wait for TRDY# in such a case.  However, even in this case, the master must assert IRDY# for at least one cycle after deasserting FRAME#.  (Commonly, a master will assert IRDY# before receiving DEVSEL#, so it must simply hold IRDY# asserted for one cycle longer.)  This is to ensure that bus turnaround timing rules are obeyed on the FRAME# line.