Editing PCI Express (section)

=== PCI Express 6.0 <span class="anchor" id="6.0"></span> ===
On 18 June 2019, PCI-SIG announced the development of PCI Express 6.0 specification. Bandwidth is expected to increase to 64{{nbsp}}GT/s, yielding 128{{nbsp}}GB/s in each direction in a 16-lane configuration, with a target release date of 2021.<ref name="businesswire.com" /> The new standard uses 4-level [[pulse-amplitude modulation]] (PAM-4) with a low-latency [[forward error correction]] (FEC) in place of [[non-return-to-zero]] (NRZ) modulation.<ref name="O5gOe" /> Unlike previous PCI Express versions, forward error correction is used to increase data integrity and PAM-4 is used as line code so that two bits are transferred per transfer. With 64{{nbsp}}GT/s data transfer rate (raw bit rate), up to 121{{nbsp}}GB/s in each direction is possible in x16 configuration.<ref name="businesswire.com" />

On 24 February 2020, the PCI Express 6.0 revision 0.5 specification (a "first draft" with all architectural aspects and requirements defined) was released.<ref name="puGmx" />

On 5 November 2020, the PCI Express 6.0 revision 0.7 specification (a "complete draft" with electrical specifications validated via test chips) was released.<ref name="ltCSi" />

On 6 October 2021, the PCI Express 6.0 revision 0.9 specification (a "final draft") was released.<ref name="60r9">{{cite web |last=Yanes |first=Al |title=PCIe® 6.0 Specification, Version 0.9: One Step Closer to Final Release {{!}} PCI-SIG |url=https://pcisig.com/blog/pcie®-60-specification-version-09-one-step-closer-final-release |website=pcisig.com |access-date=6 October 2021}}</ref>

On 11 January 2022, PCI-SIG officially announced the release of the final PCI Express 6.0 specification.<ref>{{cite web|url=https://www.businesswire.com/news/home/20220111005011/en/PCI-SIG%C2%AE-Releases-PCIe%C2%AE-6.0-Specification-Delivering-Record-Performance-to-Power-Big-Data-Applications |title=PCI-SIG® Releases PCIe® 6.0 Specification Delivering Record Performance to Power Big Data Applications |publisher=Business Wire |date=2022-01-11 |accessdate=2022-02-16}}</ref>

[[PAM-4]] coding results in a vastly higher [[bit error rate]] (BER) of 10<sup>−6</sup> (vs. 10<sup>−12</sup> previously), so in place of 128b/130b encoding, a 3-way interlaced [[forward error correction]] (FEC) is used in addition to [[cyclic redundancy check]] (CRC). A fixed 256 byte [[Flit (computer networking)|Flow Control Unit]] (FLIT) block carries 242 bytes of data, which includes variable-sized transaction level packets (TLP) and data link layer payload (DLLP); remaining 14 bytes are reserved for 8-byte CRC and 6-byte FEC.<ref name=pcie6_evolution_blog>{{cite web|url=https://pcisig.com/blog/evolution-pci-express-specification-its-sixth-generation-third-decade-and-still-going-strong |title=The Evolution of the PCI Express Specification: On its Sixth Generation, Third Decade and Still Going Strong |publisher=Pci-Sig |date=2022-01-11 |accessdate=2022-02-16}}</ref><ref name="PCIe6_fut">{{cite web|url=https://www.youtube.com/watch?v=jhehXwnu0Ss | archive-url=https://ghostarchive.org/varchive/youtube/20211030/jhehXwnu0Ss| archive-date=2021-10-30|title=PCIe 6.0 Specification: The Interconnect for I/O Needs of the Future |page=8 |author=Debendra Das Sharma | date=8 June 2020|publisher=PCI-SIG}}{{cbignore}}</ref> 3-way [[Gray code]] is used in PAM-4/FLIT mode to reduce error rate; the interface does not switch to NRZ and 128/130b encoding even when retraining to lower data rates.<ref name=cadence_pice6>{{cite web|url=https://www.cadence.com/content/dam/cadence-www/global/en_US/documents/tools/ip/design-ip/pushing-the-envelope-with-pcie-6-wp.pdf |title=Pushing the Envelope with PCIe 6.0: Bringing PAM4 to PCIe |date= |accessdate=2022-02-16}}</ref><ref name=pcie6_webinar>{{cite web|url=https://pcisig.com/sites/default/files/files/PCIe%206.0%20Webinar_Final_.pdf |title=PowerPoint Presentation |date= |accessdate=2022-02-16}}</ref>