Editing X86 (section)

==={{vanchor|SSE}} and AVX===
{{Main|Streaming SIMD Extensions|SSE2|SSE3|SSSE3|SSE4|SSE5}}

In 1999, Intel introduced the Streaming SIMD Extensions (SSE) [[instruction set]], following in 2000 with SSE2. The first addition allowed offloading of basic floating-point operations from the x87 stack and the second made MMX almost obsolete and allowed the instructions to be realistically targeted by conventional compilers. Introduced in 2004 along with the [[Intel Prescott|''Prescott'']] revision of the [[Pentium 4]] processor, SSE3 added specific memory and [[Thread (computing)|thread]]-handling instructions to boost the performance of Intel's [[HyperThreading]] technology. AMD licensed the SSE3 instruction set and implemented most of the SSE3 instructions for its revision E and later Athlon 64 processors. The Athlon 64 does not support HyperThreading and lacks those SSE3 instructions used only for HyperThreading.<ref name="tomshardware">{{cite news |title=Upgrading And Repairing PCs 21st Edition: Processor Features |url=https://www.tomshardware.com/reviews/processors-cpu-apu-features-upgrade,3569-3.html |access-date=5 June 2022 |work=Tom's Hardware |date=31 October 2013 |language=en}}</ref>

SSE discarded all legacy connections to the FPU stack. This also meant that this instruction set discarded all legacy connections to previous generations of SIMD instruction sets like MMX. But it freed the designers up, allowing them to use larger registers, not limited by the size of the FPU registers. The designers created eight 128-bit registers, named XMM0 through XMM7. (In [[x86-64|AMD64]], the number of SSE XMM registers has been increased from 8 to 16.) However, the downside was that operating systems had to have an awareness of this new set of instructions in order to be able to save their register states. So Intel created a slightly modified version of Protected mode, called Enhanced mode which enables the usage of SSE instructions, whereas they stay disabled in regular Protected mode. An OS that is aware of SSE will activate Enhanced mode, whereas an unaware OS will only enter into traditional Protected mode.

SSE is a SIMD instruction set that works only on floating-point values, like 3DNow!. However, unlike 3DNow! it severs all legacy connection to the FPU stack. Because it has larger registers than 3DNow!, SSE can pack twice the number of [[single precision]] floats into its registers. The original SSE was limited to only single-precision numbers, like 3DNow!. The SSE2 introduced the capability to pack [[double precision]] numbers too, which 3DNow! had no possibility of doing since a double precision number is 64-bit in size which would be the full size of a single 3DNow! MMn register. At 128&nbsp;bits, the SSE XMMn registers could pack two double precision floats into one register. Thus SSE2 is much more suitable for scientific calculations than either SSE1 or 3DNow!, which were limited to only single precision. SSE3 does not introduce any additional registers.<ref name="tomshardware" />

{{main|Advanced Vector Extensions|AVX-512}}
The Advanced Vector Extensions (AVX) doubled the size of SSE registers to 256-bit YMM registers. It also introduced the VEX coding scheme to accommodate the larger registers, plus a few instructions to permute elements. AVX2 did not introduce extra registers, but was notable for the addition for masking, [[Gather-scatter (vector addressing)|gather]], and shuffle instructions.

AVX-512 features yet another expansion to 32 512-bit ZMM registers and a new EVEX scheme. Unlike its predecessors featuring a monolithic extension, it is divided into many subsets that specific models of CPUs can choose to implement.