Editing System on a chip (section)

== Fabrication ==
{{More citations needed section|date=March 2017}}{{See|Semiconductor device fabrication}}

SoC chips are typically [[semiconductor device fabrication|fabricated]] using [[metal–oxide–semiconductor]] (MOS) technology.<ref>{{cite book |last1=Lin |first1=Youn-Long Steve |title=Essential Issues in SOC Design: Designing Complex Systems-on-Chip |date=2007 |publisher=[[Springer Science & Business Media]] |isbn=978-1-4020-5352-8 |page=176 |url=https://books.google.com/books?id=7OV9lEn9LiQC&pg=PA176}}</ref> The netlists described above are used as the basis for the physical design ([[place and route]]) flow to convert the designers' intent into the design of the SoC. Throughout this conversion process, the design is analyzed with static timing modeling, simulation and other tools to ensure that it meets the specified operational parameters such as frequency, power consumption and dissipation, functional integrity (as described in the register transfer level code) and electrical integrity.

When all known bugs have been rectified and these have been re-verified and all physical design checks are done, the physical design files describing each layer of the chip are sent to the foundry's mask shop where a full set of glass lithographic masks will be etched. These are sent to a wafer fabrication plant to create the SoC dice before packaging and testing.

SoCs can be fabricated by several technologies, including:
* [[Full custom]] [[ASIC]]
* [[Standard cell]] ASIC
* [[Field-programmable gate array]] (FPGA)

ASICs consume less power and are faster than FPGAs but cannot be reprogrammed and are expensive to manufacture. FPGA designs are more suitable for lower volume designs, but after enough units of production ASICs reduce the total cost of ownership.<ref>{{Cite web|url=https://numato.com/blog/differences-between-fpga-and-asics/|title=FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=July 17, 2018 |language=en-US|access-date=2018-10-17}}</ref>

SoC designs consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. With fewer packages in the system, assembly costs are reduced as well.

However, like most [[very-large-scale integration]] (VLSI) designs, the total cost{{Clarify|reason=what kind of cost?|date=May 2018}} is higher for one large chip than for the same functionality distributed over several smaller chips, because of [[Semiconductor device fabrication#Device test|lower yields]]{{Clarify|reason=confusing to non-experts|date=May 2018}} and higher [[non-recurring engineering]] costs.

When it is not feasible to construct an SoC for a particular application, an alternative is a [[system in package]] (SiP) comprising a number of chips in a single [[chip carrier|package]]. When produced in large volumes, SoC is more cost-effective than SiP because its packaging is simpler.<ref>{{cite magazine |magazine=[[EE Times]] |url=https://www.eetimes.com/the-great-debate-soc-vs-sip/ |title=The Great Debate: SOC vs. SIP |date=March 21, 2005 |access-date=July 28, 2015}}</ref> Another reason SiP may be preferred is [[waste heat]] may be too high in a SoC for a given purpose because functional components are too close together, and in an SiP heat will dissipate better from different functional modules since they are physically further apart.