Editing Very long instruction word (section)

== Design ==

In superscalar designs, the number of execution units is invisible to the instruction set. Each instruction encodes one operation only. For most superscalar designs, the instruction width is 32 bits or fewer.

In contrast, one VLIW instruction encodes multiple operations, at least one operation for each execution unit of a device. For example, if a VLIW device has five execution units, then a VLIW instruction for the device has five operation fields, each field specifying what operation should be done on that corresponding execution unit. To accommodate these operation fields, VLIW instructions are usually at least 64 bits wide, and far wider on some architectures.

For example, the following is an instruction for the [[Super Harvard Architecture Single-Chip Computer]] (SHARC). In one cycle, it does a floating-point multiply, a floating-point add, and two autoincrement loads. All of this fits in one 48-bit instruction:

<code>f12 = f0 * f4, f8 = f8 + f12, f0 = dm(i0, m3), f4 = pm(i8, m9);</code>

Since the earliest days of computer architecture,<ref>{{cite web|title=Control Data 6400/6500/6600 Computer Systems Reference Manual|url=http://ed-thelen.org/comp-hist/CDC-6600-R-M.html|access-date=2013-11-07|date=1969-02-21|url-status=dead|archive-url=https://web.archive.org/web/20140102194752/http://ed-thelen.org/comp-hist/CDC-6600-R-M.html|archive-date=2014-01-02}}</ref> some CPUs have added several [[arithmetic logic unit]]s (ALUs) to run in parallel. [[Superscalar]] CPUs use hardware to decide which operations can run in parallel at runtime, while VLIW CPUs use software (the compiler) to decide which operations can run in parallel in advance. Because the complexity of instruction scheduling is moved into the compiler, complexity of hardware can be reduced substantially.{{clarify|date=May 2016|reason=Please quantity this, as a factor or fraction or percentage, of area or cost or some other useful variable.}}

A similar problem occurs when the result of a parallelizable instruction is used as input for a branch. Most modern CPUs ''guess'' which branch will be taken even before the calculation is complete, so that they can load the instructions for the branch, or (in some architectures) even start to [[speculative execution|compute them speculatively]]. If the CPU guesses wrong, all of these instructions and their context need to be ''[[pipeline flush |flushed]]'' and the correct ones loaded, which takes time.

This has led to increasingly complex instruction-dispatch [[branch predictor | logic that attempts to guess correctly]], and the simplicity of the original [[reduced instruction set computing]] (RISC) designs has been eroded. VLIW lacks this logic, and thus lacks its energy use, possible design defects, and other negative aspects.

In a VLIW, the compiler uses heuristics or [[profile-guided optimization | profile information to guess]] the direction of a branch. This allows it to move and preschedule operations speculatively before the branch is taken, favoring the most likely path it expects through the branch. If the branch takes an unexpected way, the compiler has already generated compensating code to discard speculative results to preserve program semantics.

[[Vector processor]] cores (designed for large [[Array (data structure)|one-dimensional arrays]] of data called ''vectors'') can be combined with the VLIW architecture such as in the Fujitsu [[FR-V]] microprocessor, further increasing [[throughput]] and [[Algorithmic efficiency#Speed|speed]].{{CN|date=July 2022}}